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R8C/15 Datasheet(PDF) 180 Page - Renesas Technology Corp

Part # R8C/15
Description  16-BIT SINGLE-CHIP MICROCOMPUTER M16C FAMILY / R8C/Tiny SERIES
PDF  277 Pages
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Manufacturer  RENESAS [Renesas Technology Corp]
Direct Link  http://www.renesas.com
Logo RENESAS - Renesas Technology Corp

R8C/15 Datasheet(HTML) 180 Page - Renesas Technology Corp

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R8C/14 Group, R8C/15 Group
16. A/D Converter
Rev.2.10
Jan 19, 2006
Page 168 of 253
REJ09B0164-0210
16. A/D Converter
The A/D converter consists of one 10-bit successive approximation A/D converter circuit with a capacitive
coupling amplifier. The analog input shares the pins with P1_0 to P1_3. Therefore, when using these pins,
ensure the corresponding port direction bits are set to “0” (input mode).
When not using the A/D converter, set the VCUT bit in the ADCON1 register to “0” (Vref unconnected), so
that no current will flow from the VREF pin into the resistor ladder, helping to reduce the power consumption
of the chip.
The result of A/D conversion is stored in the AD register.
Table 16.1 lists the Performance of A/D converter. Figure 16.1 shows the Block Diagram of A/D Converter.
Figures 16.2 and 16.3 show the A/D converter-related registers.
NOTES:
1. Analog input voltage does not depend on use of sample and hold function.
2. The frequency of
φAD must be 10 MHz or below.
Without sample and hold function, the
φAD frequency should be 250 kHz or above.
With the sample and hold function, the
φAD frequency should be 1 MHz or above.
3. In repeat mode, only 8-bit mode can be used.
Table 16.1
Performance of A/D converter
Item
Performance
A/D Conversion Method
Successive approximation (with capacitive coupling amplifier)
Analog Input Voltage(1)
0V to Vref
Operating Clock
φAD(2)
4.2V
≤ AVCC ≤ 5.5V f1, f2, f4
2.7V
≤ AVCC < 4.2V f2, f4
Resolution
8 bit or 10 bit is selectable
Absolute Accuracy
AVCC = Vref = 5V
• 8-bit resolution ±2 LSB
• 10-bit resolution ±3 LSB
AVCC = Vref = 3.3 V
• 8-bit resolution ±2 LSB
• 10-bit resolution ±5 LSB
Operating Mode
One-shot and repeat modes(3)
Analog Input Pin
4 pins (AN8 to AN11)
A/D Conversion Start Condition • Software trigger
Set the ADST bit in the ADCON0 register to “1” (A/D conversion
starts)
•Capture
Timer Z interrupt request is generated while the ADST bit is set to “1”
Conversion Rate Per Pin
• Without sample and hold function
8-bit resolution: 49
φAD cycles, 10-bit resolution: 59φAD cycles
• With sample and hold function
8-bit resolution: 28
φAD cycles, 10-bit resolution: 33φAD cycles



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