R8CSLASH15 datasheet(177/277 Pages) RENESAS

177 / 277 page

R8C/14 Group, R8C/15 Group

15. Clock Synchronous Serial I/O with Chip Select (SSU)

Rev.2.10

Jan 19, 2006

Page 165 of 253

REJ09B0164-0210

15.6.3

Data Receive

Figure 15.19 shows an example of the SSU operation for the data receive. During the data receive,

the SSU operates as described below.

When the SSU is set as a master device, it outputs a synchronous clock and inputs data. When the

SSU is set as a salve device, it outputs data synchronized with the input clock while the SCS pin is

held “L” input. When the SSU is set as a master device, it outputs a receive clock and starts receiving

by performing dummy read on the SSRDR register.

After the 8-bit data is received, the RDRF bit in the SSSR register is set to “1” (data in the SSRDR

set to “1” (enables RXI and OEI interrupt request), the RXI interrupt request is generated. If the

SSRDR register is read, the RDRF bit is automatically set to “0” (no data in the SSRDR register).

Read the receive data after setting the RSSTP bit in the SSCRH register to “1” (after receiving 1-byte

data, the receive operation is completed). The SSU outputs a clock for receiving 8-bit data and stops.

After that, set the RE bit in the SSER register to “0” (disables receive) and the RSSTP bit to “0”

(receive operation is continued after receiving 1-byte data) and read the receive data. If the SSRDR

When the 8th clock rises while the RDRF bit is set to “1”, the ORER bit in the SSSR register is set to

“1” (overrun error occurs : OEI) and the operation is stopped. When the ORER bit is set to “1”, receive

can not be performed. Confirm that the ORER bit is set to “0” before restarting receive.

When the RDRF and ORER bits are set to “1”, it varies depending on setting the CPHS bit in the

SSMR register. Figure 15.19 shows when the RDRF and ORER bits are set to “1”.

When the CPHS bit is set to “1” (data download at the odd edges), the RDRF and ORER bits are set

to “1” at one point of a frame.

A sample flowchart is the same as the clock synchronous communication mode (Refer to Figure

15.15 Sample Flowchart for Data Receive (MSS=1) (Clock Synchronous Communication

Mode)

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