R8CSLASH15 datasheet(173/277 Pages) RENESAS

173 / 277 page

R8C/14 Group, R8C/15 Group

15. Clock Synchronous Serial I/O with Chip Select (SSU)

Rev.2.10

Jan 19, 2006

Page 161 of 253

REJ09B0164-0210

15.6

Operation in 4-Wire Bus Communication Mode

4-wire bus communication mode is a mode which communicates with the 4-wire bus; a clock line, data

input line, data output line and chip select line. This mode includes bidirectional mode in which the data

input line and data output line function as a single pin.

The data input line and output line are changed according to the setting of the MSS bit in the SSCRH

I/O Pin and SS Shift Register

. In this mode, association between the clock polarity, phase and data can

be set by the CPOS and CPHS bits in the SSMR register. For details, refer to 15.1.1 Association

between Transfer Clock Polarity, Phase and Data

When the SSU is set as a master device, the chip select line controls output. When the SSU is set as a

slave device, the chip select line controls input. When the SSU is set as master device, the chip select

line controls output of the SCS pin or controls output of a general port by setting the CSS1 bit in the

SSMR2 register. When the SSU is set as a slave device, the chip select line set the SCS pin as an input

pin by setting the CSS1 and CSS0 bits in the SSMR2 register to “01b”.

In 4-wire bus communication mode, the MLS bit in the SSMR register is set to “0” and communication is

performed using the MSB-first.

15.6.1

Initialization in 4-Wire Bus Communication Mode

Figure 15.17 shows an Initialization in 4-Wire Bus Communication Mode. Before the data transit/

receive, set the TE bit in the SSER register to “0” (disables transmit) and the RE bit in the SSER

When communication mode and format are changed, set the TE bit to “0” and the RE bit to “0” before

changing.

Setting the RE bit to “0” does not change the contents of the RDRF and ORER flags, and the contents

of the SSRDR register.

R8C/15 Datasheet(PDF) 173 Page - Renesas Technology Corp