R8CSLASH15 datasheet(171/277 Pages) RENESAS

171 / 277 page

R8C/14 Group, R8C/15 Group

15. Clock Synchronous Serial I/O with Chip Select (SSU)

Rev.2.10

Jan 19, 2006

Page 159 of 253

REJ09B0164-0210

15.5.4

Data Transmit/Receive

Data transmit/receive is a combined operation of data transmit and receive which are described

before. Transmit/receive is started by writing data in the SSTDR register.

When the 8th clock rises or the ORER bit is set to “1” (overrun error occurs) while the TDRE bit is set

to “1” (data is transferred from the SSTDR to SSTRSR registers), the transmit/receive operation is

stopped.

When switching from transmit mode (TE=1) or receive mode (RE=1) to transmit/receive mode

(Te=RE=1), set the TE bit to “0” and RE bit to “0” before switching. After confirming that the TEND bit

is set to “0” (the TDRE bit is set to “0” when the last bit of the transmit data is transmitted), the RERF

bit is set to “0” (no data in the SSRDR register) and the ORER bit is set to “0” (no overrun error), set

the TE and RE bits to “1”.

When setting the microcomputer to the slave device, ensure the TEND bit is set to “1” (data transmit

ends) and write the following transmit data to the SSTDR register. When setting the microcomputer to

the master device, continuous transmit is enabled.

Figure 15.16 shows a Sample Flowchart for Data Transmit/Receive (Clock Synchronous

Communication Mode).

R8C/15 Datasheet(PDF) 171 Page - Renesas Technology Corp