R8CSLASH15 datasheet(169/277 Pages) RENESAS

169 / 277 page

R8C/14 Group, R8C/15 Group

15. Clock Synchronous Serial I/O with Chip Select (SSU)

Rev.2.10

Jan 19, 2006

Page 157 of 253

REJ09B0164-0210

15.5.3

Data Receive

Figure 15.14 shows an Example of Operation for Data Receive (Clock Synchronous Communication

Mode).

During the data receive, the SSU operates as described below. When the SSU is set as a master

device, it outputs a synchronous clock and inputs data.

When the SSU is set as a salve device, it outputs data synchronized with the input clock. When the

SSU is set as a master device, it outputs a receive clock and starts receiving by performing dummy

read on the SSRDR register.

After the 8-bit data is received, the RDRF bit in the SSSR register is set to “1” (data in the SSRDR

set to “1” (enables RXI and OEI interrupt request), the RXI interrupt request is generated. If the SSDR

Read the receive data after setting the RSSTP bit in the SSCRH register to “1” (after receiving 1-byte

data, the receive operation is completed). The SSU outputs a clock for receiving 8-bit data and stops.

After that, set the RE bit in the SSER register to “0” (disables receive) and the RSSTP bit to “0”

(receive operation is continued after receiving the 1-byte data) and read the receive data. If the

SSRDR register is read while the RE bit is set to “1” (enables receive), a receive clock is output again.

When the 8th clock rises while the RDRF bit is set to “1”, the ORER bit in the SSSR register is set to

“1” (overrun error occurs : OEI) and the operation is stopped. When the ORER bit is set to “1”, receive

can not be performed. Confirm that the ORER bit is set to “0” before restarting receive.

Figure 15.15 shows a Sample Flowchart for Data Receive (MSS=1) (Clock Synchronous

Communication Mode).

Figure 15.14

Example of Operation for Data Receive (Clock Synchronous Communication Mode)

SSCK

SSI

• When SSUMS=0 (clock synchronous communication mode), CPHS=0 (data download

at even edges) and CPOS bit=0 (“H” when clock stops)

1 Frame

RDRF Bit in

SSSR Register

“0”

“1”

RSSTP Bit in

SSCRH Register “0”

“1”

Dummy read in

SSRDR register

Process by

program

RXI interrupt request

generation

1 Frame

RXI interrupt request

generation

Read data in SSRDR

Read data in

SSRDR register

Set RSSTP bit to “1”

RXI interrupt request

generation

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