R8CSLASH15 datasheet(172/277 Pages) RENESAS

172 / 277 page

R8C/14 Group, R8C/15 Group

15. Clock Synchronous Serial I/O with Chip Select (SSU)

Rev.2.10

Jan 19, 2006

Page 160 of 253

REJ09B0164-0210

Figure 15.16

Sample Flowchart for Data Transmit/Receive (Clock Synchronous Communication

Mode)

Start

Initialization

Read TDRE bit in SSSR register

SSSR register

TEND bit

← 0(1)

End

TDRE=1 ?

Write transmit data to SSTDR register

Data transmit

continued?

Yes

SSER register

RE bit

← 0

TE bit

← 0

(1)

(2)

(3)

(1) After reading the SSSR register and confirming

that the TDRE bit is set to “1”, write the transmit

data in the SSTDR register. When writing the

transmit data to the SSTDR register, the TDRE bit

is automatically set to “0”.

(5) Set the TEND bit to “0” and the RE and TE bits in

(6) the SSER register to “0” before ending transmit/

receive mode.

Read receive data in SSRDR register

Read RDRF bit in SSSR register

RDRF=1 ?

Yes

(4)

(2) Confirm that the RDRF bit is set to “1”. If the

RDRF bit is set to “1”, read the receive data in the

SSRDR register. When reading the SSRDR

(3) Determine whether the transmit data is continued.

(5)

NOTES:

1. Write “0” after reading “1” to set the TEND bit to “0”.

Read TEND bit in SSSR register

TEND=1 ?

Yes

(6)

(4) When the data transmit is completed, the TEND

bit in the SSSR register is set to “1”.

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