R8CSLASH15 datasheet(175/277 Pages) RENESAS

175 / 277 page

R8C/14 Group, R8C/15 Group

15. Clock Synchronous Serial I/O with Chip Select (SSU)

Rev.2.10

Jan 19, 2006

Page 163 of 253

REJ09B0164-0210

15.6.2

Data Transmit

Figure 15.18 shows an Example of Operation in Data Transmit (4-Wire Bus Communication Mode).

During the data transmit, the SSU operates as described below.

When the SSU is set as a master device, it outputs a synchronous clock and data. When the UUSA is

set as a slave device, it outputs data in synchronized with the input clock while “L” applies to the SCS

pin.

When writing the transmit data to the SSTDR register after setting the TE bit to “1” (enables transmit),

the TDRE bit is automatically set to “0” (data is not transferred from the SSTDR to SSTRSR registers)

and the data is transferred from the SSTDR to SSTRSR registers. After the TDRE bit is set to “1”

(data is transferred from the SSTDR to SSTRSR registers), a transmit is started. When the TIE bit in

the SSER register is set to “1”, the TXI interrupt request is generated.

When the 1-frame data is transferred while the TDRE bit is set to “0”, the data is transferred from the

SSTDR to SSTRSR registers and the next frame transmit is started. If the 8th bit is transmitted while

the TDRE is set to “1”, the TEND in the SSSR register is set to “1” (when the last bit of the transmit

data is transmitted, the TDRE bit is set to “1”) and the state is retained. If the TEIE bit in the SSER

The SSCK pin is retained “H” after transmit-end and the SCS pin is held “H”. When the SCS pin is

transmitted When transmitting continuously while the SCS pin is held “L”, write the next transmit data

to the SSTDR register before transmitting the 8th bit.

Transmit can not be performed while the ORER bit in the SSSR register is set to “1” (overrun error

occurs). Confirm that the ORER bit is set to “0” before transmit.

When setting the microcomputer to the slave device, ensure the TEND bit is set to “1” (data transmit

ends) and write the following transmit data to the SSTDR register. When setting the microcomputer to

the master device, continuous transmit is enabled.

The difference from the clock synchronous communication mode is that the SSO pin is placed in

high-impedance state while the SCS pin is placed in high-impedance state when operating as a

master device and the SSI pin is placed in high-impedance state while the SCS pin is placed in “H”

input state when operating as a slave device.

A sample flowchart is the same as the clock synchronous communication mode (Refer to Figure

15.13 Sample Flowchart for Data Transmit (Clock Synchronous Communication Mode)

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