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R8C/15 Datasheet(PDF) 174 Page - Renesas Technology Corp |
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R8C/15 Datasheet(HTML) 174 Page - Renesas Technology Corp |
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174 / 277 page ![]() R8C/14 Group, R8C/15 Group 15. Clock Synchronous Serial I/O with Chip Select (SSU) Rev.2.10 Jan 19, 2006 Page 162 of 253 REJ09B0164-0210 Figure 15.17 Initialization in 4-Wire Bus Communication Mode Start SSMR2 register SSUMS bit ← 1 SSCRH register Set CKS0 to CKS2 bits SSSR register ORER bit ← 0(1) SSER register RE bit ← 1 (when receive) TE bit ← 1 (when transmit) Set RIE, TEIE and TIE bits End SSER register RE bit ← 0 TE bit ← 0 SSCRH register Set RSSTP bit (2) Set the BIDE bit to “1” in bidirectional mode and the I/O of the #SCS pin is set by the CSSO to CSS1 bits. (1) (1) The MLS bit is set to “0” for the MSB-first transfer. The clock polarity and phase are set by the CPHS and CPOS bits. (2) NOTES: 1. Write “0” after reading “1” to set the ORER bit to “0”. SSMR2 register SCKS bit ← 1 Set SOOS, CSS to CSS1 and BIDE bits SSCRH register Set MSS bit SSMR register Set CPHS and CPOS bits MLS bits ← 0 |
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