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R8C/15 Datasheet(PDF) 178 Page - Renesas Technology Corp |
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R8C/15 Datasheet(HTML) 178 Page - Renesas Technology Corp |
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178 / 277 page ![]() R8C/14 Group, R8C/15 Group 15. Clock Synchronous Serial I/O with Chip Select (SSU) Rev.2.10 Jan 19, 2006 Page 166 of 253 REJ09B0164-0210 Figure 15.19 Example of Operation in Data Receive (4-Wire Bus Communication Mode) SSCK b0 SSI • When CPHS bit=0 (data download at even edges) and CPOS bit=0 (“H” when clock stops) b7 SCS (Output) SSCK • When CPHS bit=1 (data download at odd edges) and CPOS bit=0 (“H” when clock stops) CPHS and CPOS : Bit in SSMR register 1 Frame RDRF Bit in SSSR Register “0” “1” RSSTP Bit in SSCRH Register “0” “1” Dummy read in SSRDR register Process by Program 1 Frame High-Impedance b0 b7 High-Impedance SCS (Output) b7 b0 Data read in SSRDR register RXI interrupt request is generated RXI interrupt request is generated Data read in SSRDR register RXI interrupt request is generated b0 b7 b0 b7 b7 b0 SSI 1 Frame RDRF Bit in SSSR Register “0” “1” RSSTP Bit in SSCRH Register “0” “1” Dummy read in SSRDR register Process by Program 1 Frame Data read in SSRDR register RXI interrupt request is generated RXI interrupt request is generated RXI interrupt request is generated Set RSSTP bit to “1” Data read in SSRDR register Set RSSTP bit to “1” |
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