R8CSLASH15 datasheet(167/277 Pages) RENESAS

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R8C/14 Group, R8C/15 Group

15. Clock Synchronous Serial I/O with Chip Select (SSU)

Rev.2.10

Jan 19, 2006

Page 155 of 253

REJ09B0164-0210

15.5.2

Data Transmit

Figure 15.12 shows an Example of SSU Operation for Data Transmit (Clock Synchronous

Communication Mode). During the data transmit, the SSU operates as described below.

When the SSU is set as a master device, it outputs a synchronous clock and data.

When the SSU is set as a slave device, it outputs data synchronized with the input clock. When

setting the TE bit to “1” (enables transmit) before writing the transmit data to the SSTDR register, the

TDRE bit is automatically set to “0” (data is not transferred from the SSTDR to SSTRSR registers)

and the data is transferred from the SSTDR to SSTRSR registers.

After the TDRE bit is set to “1” (data is transferred from the SSTDR to SSTRSR registers), a transmit

is started. When the TIE bit in the SSER register is set to “1”, the TXI interrupt request is generated.

When one frame of data is transferred while the TDRE bit is set to “0”, data is transferred from the

SSTDR to SSTRSR registers and a transmit of the next frame is started. If the 8th bit is transmitted

while the TDRE bit is set to “1”, the TEND bit in the SSSR register is set to “1” (the TDRE bit is set to

“1” when the last bit of the transmit data is transmitted) and the state is retained. The TEI interrupt

request is generated when the TEIE bit in the SSER register is set to “1” (enables transmit-end

interrupt request). The SSCK pin is retained “H” after transmit-end.

Transmit can not be performed while the ORER bit in the SSRR register is set to “1” (overrun error

occurs). Confirm that the ORER bit is set to “0” before transmit.

When setting the microcomputer to the slave device, ensure the TEND bit is set to “1” (data transmit

ends) and write the following transmit data to the SSTDR register. When setting the microcomputer to

the master device, continuous transmit is enabled.

Figure 15.13 shows a Sample Flowchart for Data Transmit (Clock Synchronous Communication

Mode).

Figure 15.12

Example of SSU Operation for Data Transmit (Clock Synchronous Communication

Mode)

SSCK

SSO

• When SSUMS=0 (clock synchronous communication mode), CPHS=0 (data change

at odd numbers) and CPOS=0 (“H” when clock stops)

1 Frame

TDRE Bit in

SSSR Register

“0”

“1”

TEND Bit in

SSSR Register

“0”

“1”

TEI interrupt request

generation

Write data to SSTDR register

Process by

Program

1 Frame

TXI interrupt request generation

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