R8CSLASH15 datasheet(247/277 Pages) RENESAS

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R8C/14 Group, R8C/15 Group

20. Precautions

Rev.2.10

Jan 19, 2006

Page 235 of 253

REJ09B0164-0210

20. Precautions

20.1

Stop Mode and Wait Mode

20.1.1

Stop Mode

When entering stop mode, set the FMR01 bit to “0” (CPU rewrite mode disabled) and the CM10 bit to

“1” (stop mode). An instruction queue pre-reads 4 bytes from the instruction which sets the CM10 bit

in the CM1 register to “1” (stop mode) and the program stops. Insert at least 4 NOP instructions after

inserting the JMP.B instruction immediately after the instruction which sets the CM10 bit to “1”.

Use the next program to enter stop mode.

• Program to enter stop mode

BCLR

1,FMR0

; CPU rewrite mode disabled

BSET

0,PRCR

; Protect disabled

BSET

0,CM1

; Stop mode

JMP.B

LABEL_001

LABEL_001 :

NOP

20.1.2

Wait Mode

When entering wait mode, set the FMR01 bit to “0” (CPU rewrite mode disabled) and execute the

WAIT instruction. An instruction queue pre-reads 4 bytes from the WAIT instruction and the program

stops. Insert at least 4 NOP instructions after the WAIT instruction.

Also, the value in the specific internal RAM area may be rewritten when exiting wait mode if writing to

the internal RAM area before executing the WAIT instruction and entering wait mode. The area for a

maximum of 3 bytes is rewritten from the following address of the internal RAM in which the writing is

performed before the WAIT instruction. The rewritten value is the same value as the one which was

written before the WAIT instruction. If this causes a problem, avoid by inserting the JMP.B instruction

between the writing instruction to the internal RAM area and WAIT instruction as shown in the

following program example.

• Example to execute the WAIT instruction

Program Example

MOV.B

#055h,0601h

; Write to internal RAM area

...

JMP.B

LABEL_001

LABEL _001 :

FSET

; Enable interrupt

BCLR

1,FMR0

; CPU rewrite mode disabled

WAIT

; Wait mode

NOP

When accessing any area other than the internal RAM area between the writing instruction to the

internal RAM area and execution of the WAIT instruction, this situation will not occur.

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