R8CSLASH15 datasheet(250/277 Pages) RENESAS

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R8C/14 Group, R8C/15 Group

20. Precautions

Rev.2.10

Jan 19, 2006

Page 238 of 253

REJ09B0164-0210

20.2.6

Changing Interrupt Control Register

(a) Each interrupt control register can only be changed while interrupt requests corresponding to

that register are not generated. If interrupt requests may be generated, disable the interrupts

before changing the interrupt control register.

(b) When changing any interrupt control register after disabling interrupts, be careful with the

instructions to be used.

When changing any bit other than IR bit

If an interrupt request corresponding to that register is generated while executing the

instruction, the IR bit may not be set to “1” (interrupt requested), and the interrupt request may

be ignored. If this causes a problem, use the following instructions to change the register.

Instructions to use: AND, OR, BCLR, BSET

When changing IR bit

If the IR bit is set to “0” (interrupt not requested), it may not be set to “0” depending on the

instruction to be used. Therefore, use the MOV instruction to set the IR bit to “0”.

programs. Refer to (b) for the change of interrupt control registers in the sample programs.

Sample programs 1 to 3 are preventing the I flag from being set to “1” (interrupt enables) before

changing the interrupt control register for reasons of the internal bus or the instruction queue buffer.

Example 1: Use NOP instructions to prevent I flag being set to “1” before interrupt control

INT_SWITCH1:

FCLR

; Disable interrupts

AND.B

#00H,0056H

; Set TXIC register to “00h”

NOP

;

NOP

FSET

; Enable interrupts

Example 2: Use dummy read to have FSET instruction wait

INT_SWITCH2:

FCLR

; Disable interrupts

AND.B

#00H,0056H

; Set TXIC register to “00h”

MOV.W MEM,R0

; Dummy read

FSET

; Enable interrupts

Example 3: Use POPC instruction to change I flag

INT_SWITCH3:

PUSHC FLG

FCLR

; Disable interrupts

AND.B

#00H,0056H

; Set TXIC register to “00h”

POPC

FLG

; Enable interrupts

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