R8CSLASH15 datasheet(248/277 Pages) RENESAS

248 / 277 page

R8C/14 Group, R8C/15 Group

20. Precautions

Rev.2.10

Jan 19, 2006

Page 236 of 253

REJ09B0164-0210

20.2

Interrupts

20.2.1

Reading Address 00000h

Do not read the address 00000h by a program. When a maskable interrupt request is acknowledged,

the CPU reads interrupt information (interrupt number and interrupt request level) from 00000h in the

interrupt sequence. At this time, the acknowledged interrupt IR bit is set to “0”.

If the address 00000h is read in a program, the IR bit for the interrupt which has the highest priority

among the enabled interrupts is set to “0”. This may cause a problem that the interrupt is canceled, or

an unexpected interrupt is generated.

20.2.2

SP Setting

Set any value in the SP before an interrupt is acknowledged. The SP is set to “0000h” after reset.

Therefore, if an interrupt is acknowledged before setting any value in the SP, the program may run

out of control.

20.2.3

External Interrupt and Key Input Interrupt

Either an “L” level or an “H” level of at least 250ns width is necessary for the signal input to the INT0

to INT3 pins and KI0 to KI3 pins regardless of the CPU clock.s

20.2.4

Watchdog Timer Interrupt

Reset the watchdog timer after a watchdog timer interrupt is generated.

R8C/15 Datasheet(PDF) 248 Page - Renesas Technology Corp