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R8C/15 Datasheet(PDF) 257 Page - Renesas Technology Corp |
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R8C/15 Datasheet(HTML) 257 Page - Renesas Technology Corp |
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257 / 277 page ![]() R8C/14 Group, R8C/15 Group 20. Precautions Rev.2.10 Jan 19, 2006 Page 245 of 253 REJ09B0164-0210 20.8 Flash Memory Version 20.8.1 CPU Rewrite Mode 20.8.1.1 Operating Speed Before entering CPU rewrite mode (EW0 mode), select 5MHz or below for the CPU clock using the CM06 bit in the CM0 register and the CM16 to CM17 bits in the CM1 register. This usage note is not needed for EW1 mode. 20.8.1.2 Instructions Inhibited Against Use The following instructions cannot be used in EW0 mode because the flash memory internal data is referenced: UND, INTO, and BRK instructions. 20.8.1.3 Interrupts Table 20.1 lists the Interrupt in EW0 Mode and Table 20.2 lists the Interrupt in EW1 Mode. NOTES: 1. Do not use the address match interrupt while the command is executed because the vector of the address match interrupt is allocated on ROM. 2. Do not use the non-maskable interrupt while Block 0 is automatically erased because the fixed vector is allocated Block 0. Table 20.1 Interrupt in EW0 Mode Mode Status When maskable interrupt request is acknowledged When watchdog timer, oscillation stop detection and voltage monitor 2 interrupt request are acknowledged EW0 During automatic erasing Any interrupt can be used by allocating a vector to RAM Once an interrupt request is acknowledged, the auto- programming or auto-erasing is forcibly stopped immediately and resets the flash memory. An interrupt process starts after the fixed period and the flash memory restarts. Since the block during the auto-erasing or the address during the auto-programming is forcibly stopped, the normal value may not be read. Execute the auto-erasing again and ensure the auto-erasing is completed normally. Since the watchdog timer does not stop during the command operation, the interrupt request may be generated. Reset the watchdog timer regularly. Automatic writing |
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