4501 datasheet(201/212 Pages) RENESAS

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3.3 List of precautions

3-32

Rev.2.01

Feb 07, 2005

4501 Group

APPENDIX

REJ09B0192-0201

(4)

A/D converter is used at the comparator mode

The analog input voltage is higher than the comparison voltage as a result of comparison, the

contents of ADF flag retains “0,” not set to “1.”

In this case, the A/D interrupt does not occur even when the usage of the A/D interrupt is enabled.

Accordingly, consider the time until the comparator operation is completed, and examine the state

of ADF flag by software. The comparator operation is completed after 8 machine cycles.

(5)

Analog input pins

Even when P20/AIN0 and P21/AIN1 are set to pins for analog input, they continue to function as P2

I/O. Accordingly, when any of them are used as these ports and others are used as analog input pins,

make sure to set the outputs of pins that are set for analog input to “1.” Also, the port input function

of the pin functions as an analog input is undefined.

(6)

TALA instruction

When the TALA instruction is executed, the low-order 2 bits of register AD is transferred to the high-

order 2 bits of register A, and simultaneously, the low-order 2 bits of register A is “0.”

(7)

Recommended operating conditions when using A/D converter

The recommended operating conditions of supply voltage and system clock frequency when using A/

D converter are different from those when not using A/D converter.

Table 3.3.3 shows the recommended operating conditions when using A/D converter.

Table 3.3.3 Recommended operating conditions (when using A/D converter)

Parameter

System clock frequency

(at ceramic resonance or

RC oscillation) (Note 2)

System clock frequency

(ceramic

resonance

selected, at external

clock input)

Condition

VDD = VRST to 5.5 V (high-speed mode)

VDD = VRST to 5.5 V (middle-speed mode)

VDD = VRST to 5.5 V (low-speed mode)

VDD = VRST to 5.5 V (default mode)

VDD = VRST to 5.5 V (high-speed mode)

VDD = VRST to 5.5 V (middle-speed mode)

VDD = VRST to 5.5 V (low-speed mode)

VDD = VRST to 5.5 V (default mode)

Limits

Min.

0.1

Max.

4.4

2.2

1.1

0.5

3.2

1.6

0.8

0.4

Unit

MHz

Typ.

Duty

40 % to 60 %

Notes 1: VRST: Detection voltage of voltage drop detection circuit.

2: The frequency at RC oscillation is affected by a capacitor, a resistor and a microcomputer. So,

set the constants within the range of the frequency limits.

3.3.7 Notes on reset

(1)

The initial value of the following registers are undefined after system is released from reset. After

system is released from reset, set initial values.

• Register Z (2 bits)

• Register D (3 bits)

• Register E (8 bits)

(2)

Power-on reset

Reset can be automatically performed at power on (power-on reset) by the built-in power-on reset

circuit. When the built-in power-on reset circuit is used, the time for the supply voltage to rise from

0 V to 2.0 V must be set to 100 µs or less. If the rising time exceeds 100 µs, connect a capacitor

between the RESET pin and VSS at the shortest distance, and input “L” level to RESET pin until the

value of supply voltage reaches the minimum operating voltage.

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