7477 datasheet(113/361 Pages) RENESAS

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HARDWARE

1-106

7470/7471/7477/7478 GROUP USER’S MANUAL

1.13 Serial I/O

2 Communication format

The half-duplex data communication or the full-duplex data communication are available for

communication.

2 Synchronous clock

The following can be selected as a synchronous clock by bit 1 of the Serial I/O control register

(SIOCON: address 00E216).

q “0” : Baud rate generator (BRG) output divided by 4

q “1” : External clock input from the SCLK pin

The BRG output is set by the baud rate generator (BRG: address 00E416), which is an 8-bit

counter dedicated to the Serial I/O. As an input clock to the BRG, f(XIN)/4 or f(XCIN)/4 (at “0”),

f(XIN)/16 or f(XCIN)/16 (at “1”) can be selected by bit 0 of the Serial I/O control register.

Notes on external clock selection

q When setting the transmit enable bit to “1” or writing data into the Transmit buffer register,

perform a write operation while the synchronous clock is at “H.”

q The shift operation of the Transmit shift register or the Receive shift register is continued while

the synchronous clock is input to the Serial I/O circuit. When the external clock is selected, stop

the synchronous clock at the end of 8 cycles. (When the internal clock is selected, the synchronous

clock stops automatically at the end of 8 cycles.)

q Set the “H” and “L” widths (TWH, TWL) of the pulse used as the external clock source to TWH,

TWL [s] > 8/(system clock [Hz]). For example, when a system clock is 8 MHz, use a clock of

500 kHz or less (duty ratio 50 %).

2 Shift clock

Usually, when a clock synchronous transfer is performed between 2 microcomputers, one microcomputer

selects the internal clock and outputs the 8 shift clock pulses generated by a start of transmit

operation from the P16/SCLK pin. The other microcomputer selects the external clock and uses the

clock input from the P16/SCLK pin as a synchronous clock.

2 Data transfer rate (baud rate)

In the clock synchronous Serial I/O, the expression for calculating a data transfer rate (baud rate),

which is the frequency of the synchronous clock is shown below.

q When the internal clock is selected (using the BRG)

Baud rate [bps] =

V1 Division ratio : Select “4” or “16” by the BRG count source selection bit.

V2 BRG set value : 0 – 255 (0016 – FF16)

q When the external clock is selected

Baud rate [bps] = Input clock frequency to SCLK pin

The BRG is an 8-bit counter dedicated to the Serial I/O, having a reload register, and divides the

count source by (n + 1) by setting the value n. As a count source, f(XIN)/4 or f(XCIN)/4 (at “0”), f(XIN)/

16 or f(XCIN)/16 (at “1”) can be selected by bit 0 of the Serial I/O control register.

f(XIN)

Division ratio

V1 ! (BRG set valueV

+ 1) ! 4

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