7477 datasheet(162/361 Pages) RENESAS

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1-155

7470/7471/7477/7478 GROUP USER’S MANUAL

HARDWARE

1.16 Oscillation circuit

1.16.2 Sub-clock oscillation circuit

In the 7471/7478 group, the sub-clock f(XCIN) is available when the P50/XCIN pin and the P51/XCOUT pin

are used as the XCIN pin and the XCOUT pin.

The power supplied to the sub-clock oscillation circuit is given through a voltage reduction regulator to

reduce power dissipation in the sub-clock mode. That is, power is reduced by reducing the voltage applied

to the VCC pin by the voltage reduction regulator. The supply voltage to this oscillation circuit can be set

to one of the 2 stages of high power mode and low power mode in bit 5 of the CPU mode register.

Notes 1: When using the sub-clock, set f(XCIN) < 50 kHz < f(XIN)/3.

2: When using the sub-clock f(XCIN) in the 7471/7478 group, set the P50-P53 pull-up control bit (bit

6) of the P1-P5 pull-up control register to “0” and disconnect the pull-up transistor of the P50/XCIN

pin and P51/XCOUT pin.

3: When using the sub-clock as the internal clock

φ, use it in one of the following states.

q Fix the XCOUT drive capacity to the high power mode (set the XCOUT drive capacity selection

bit of the CPU mode register to “1”).

q When fixing the XCOUT drive capacity to the Low power mode (set the XCOUT drive capacity

selection bit of the CPU mode register to “0”), lower the value of the resistor Rd

+ in the sub-

clock oscillation circuit to a level at which the oscillation of f(XCIN) does not stop.

+ “Resistor Rd”: Refer to the circuit example in “Chapter 2 Application, 2.7 Oscillation circuit.”

7477 Datasheet(PDF) 162 Page - Renesas Technology Corp