7477 datasheet(290/361 Pages) RENESAS

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7470/7471/7477/7478 GROUP USER’S MANUAL

3-4

APPENDIX

3.1 Control registers

Fig. 3.1.5 Structure of Input latch register

Fig. 3.1.6 Structure of A-D control register

Nothing is allocated for these bits. These

are write disabled bits and are undefined at

reading.

b7 b6 b5 b4 b3 b2 b1 b0

Name

Function

At reset

Input latch register (ILR) [Address

P30/INT0 latch bit

Input latch register

P31/INT1 latch bit

P32/CNTR0 latch bit

P33/CNTR1 latch bit

When b0 of EG (Note) is “0”:

reverse level on INT0 pin

When b0 of EG (Note) is “1”:

level on INT0 pin

When b1 of EG (Note) is “0”:

reverse level on INT1 pin

When b1 of EG (Note) is “1”:

level on INT1 pin

When b2 of EG (Note) is “0”:

reverse level on CNTR 0 pin

When b2 of EG (Note) is “1”:

level on CNTR0 pin

When b3 of EG (Note) is “0”:

reverse level on CNTR 1 pin

When b3 of EG (Note) is “1”:

level on CNTR1 pin

Note: EG is the Edge polarity selection register.

00D616]

b7 b6 b5 b4 b3 b2 b1 b0

A-D control register (ADCON) [Address

At reset

R W

A-D control register

5, 6

00 0

Name

Function

A-D input selection

bits

0 0 0 : P20/IN0

0 : Under conversion

1 : End conversion

b2 b1 b0

(Note 1)

A-D conversion end

bit

(Note 2)

VREF connection

selection bit

VThe 7477/7478 group is not

provided with this bit.

This bit is undefined at

reset.

Nothing is allocated for these bits.

These are write disabled bits and are

undefined at reading.

Fix this bit to “0.”

?? !

0 0 1 : P21/IN1

0 1 0 : P22/IN2

0 1 1 : P23/IN3

1 0 0 : P24/IN4

1 0 1 : P25/IN5

1 1 0 : P26/IN6

1 1 1 : P27/IN7

0 : The VREF pin is

separated from the

comparison voltage

generator.

1 : The VREF pin is

connected to

comparison voltage

generator.

Notes 1:

Since the 7470/7477 group is not provided with pins

P24–P27, do not set.

•A-D conversion is started by setting bit 3 to “0.”

•Writing “0” into bit 3 is valid. Even if “1” is written into

bit 3, this bit is not set to “1.” Accordingly, when writing a

value into the A-D control register without affecting bit 3,

set bit 3 to “1.”

00D916]

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