CS42L52 datasheet(7/82 Pages) CIRRUS

7 / 82 page

DS680F1

CS42L52

5/13/08

8.2 Auto Detect Disabled ...................................................................................................................... 76

9. PCB LAYOUT CONSIDERATIONS ..................................................................................................... 77

9.1 Power Supply, Grounding ............................................................................................................... 77

9.2 QFN Thermal Pad .......................................................................................................................... 77

10. ADC & DAC DIGITAL FILTERS ........................................................................................................ 78

11. PARAMETER DEFINITIONS .............................................................................................................. 79

12. PACKAGE DIMENSIONS .................................................................................................................. 80

THERMAL CHARACTERISTICS .......................................................................................................... 80

13. ORDERING INFORMATION .............................................................................................................. 81

14. REFERENCES .................................................................................................................................... 81

15. REVISION HISTORY .......................................................................................................................... 81

LIST OF FIGURES

Figure 1. Typical Connection Diagram ...................................................................................................... 10

Figure 2. Headphone Output Test Load .................................................................................................... 19

Figure 3. Serial Audio Interface Timing ..................................................................................................... 21

Figure 4. Control Port Timing - I²C ............................................................................................................ 22

Figure 5. Analog Input Signal Flow ........................................................................................................... 26

Figure 6. Single-Ended MIC Configuration ............................................................................................... 27

Figure 7. Differential MIC Configuration .................................................................................................... 27

Figure 8. ALC ............................................................................................................................................ 28

Figure 9. Noise Gate Attenuation .............................................................................................................. 28

Figure 10. DSP Engine Signal Flow .......................................................................................................... 29

Figure 11. PWM Output Stage .................................................................................................................. 30

Figure 12. Analog Output Stage ................................................................................................................ 30

Figure 13. Beep Configuration Options ..................................................................................................... 31

Figure 14. Peak Detect & Limiter .............................................................................................................. 32

Figure 15. Battery Compensation ............................................................................................................. 34

Figure 16. I²S Format ................................................................................................................................ 36

Figure 17. Left-Justified Format ................................................................................................................ 36

Figure 18. Right-Justified Format (DAC only) ........................................................................................... 36

Figure 19. DSP Mode Format) .................................................................................................................. 36

Figure 20. Control Port Timing, I²C Write .................................................................................................. 38

Figure 21. Control Port Timing, I²C Read .................................................................................................. 38

Figure 22. THD+N vs. Output Power per Channel at 1.8 V (16

Ω load) ................................................... 74

Figure 23. THD+N vs. Output Power per Channel at 2.5 V (16

Ω load) ................................................... 74

Figure 24. THD+N vs. Output Power per Channel at 1.8 V (32

Ω load) ................................................... 75

Figure 25. THD+N vs. Output Power per Channel at 2.5 V (32

Ω load) ................................................... 75

Figure 26. ADC Passband Ripple ............................................................................................................. 78

Figure 27. ADC Stopband Rejection ......................................................................................................... 78

Figure 28. ADC Transition Band ............................................................................................................... 78

Figure 29. ADC Transition Band (Detail) ................................................................................................... 78

Figure 30. DAC Passband Ripple ............................................................................................................. 78

Figure 31. DAC Stopband ......................................................................................................................... 78

Figure 32. DAC Transition Band ............................................................................................................... 78

Figure 33. DAC Transition Band (Detail) ................................................................................................... 78

CS42L52 Datasheet(PDF) 7 Page - Cirrus Logic

CS42L52 Datasheet(HTML) 7 Page - Cirrus Logic

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82

Datasheet Download

Link URL