AM3892 datasheet(102/299 Pages) TI

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AM3894

AM3892

SPRS681A – OCTOBER 2010 – REVISED MARCH 2011

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Device Configurations

4.1

Control Module

The device control module includes status and control logic not addressed within the peripherals or the

remainder of the device infrastructure. This module is the primary point of control for the following areas of

the device:

•

Functional I/O multiplexing

•

Device status

•

Static device configuration

•

OCP interface for standard and customer programmable e-Fuse bit shift registers.

The control module primarily implements a bank of registers accessible (read/write) by the software along

with some read-only registers carrying status information. Most register bits are exported as control

signals for other logic blocks on the device. Certain control module registers have default values based

upon the device type as decoded from e-Fuse.

The read/write registers can be divided into the following classes:

•

Static device configuration registers

•

Status and configuration registers

•

Boot registers

Table 4-1 shows the general register groupings and Table 4-2 through Table 4-4 provide register

summaries for each group.

Table 4-1. Control Module Register Map

ADDRESS OFFSET

SEE

0x0000 - 0x0020

OCP Configuration registers

Table 4-2

0x0024 - 0x003C

Reserved

0x0040 – 0x00FC

Device Boot registers

Table 4-6

0x0300 - 0x03FC

Reserved

0x0400 - 0x05FC

PLL Control registers

Table 4-3

0x0600 - 0x07FC

Device Configuration registers

Table 4-4

0x0800 - 0x0FFC

PAD Control registers

Section 4.4

Table 4-2. OCP Configuration Registers Summary

HEX ADDRESS

ACRONYM

0x4814 0000

CONTROL_REVISION

Control module Revision number

0x4814 0004 - 0x4814 000C

Reserved

0x4814 0010

CONTROL_SYSCONFIG

Idle mode parameters

0x4814 0014 - 0x4814 003C

Reserved

Table 4-3. PLL Control Registers Summary

HEX ADDRESS

ACRONYM

0x4814 0400

MAINPLL_CTRL

Main PLL base frequency control

0x4814 0404

MAINPLL_PWD

Main PLL clock output powerdown

0x4814 0408

MAINPLL_FREQ1

Main Clock 1 fractional divider

0x4814 040C

MAINPLL_DIV1

Main Clock 1 post divider

0x4814 0410

MAINPLL_FREQ2

Main Clock 2 fractional divider

0x4814 0414

MAINPLL_DIV2

Main Clock 2 post divider

102

Device Configurations

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