AM3892 datasheet(106/299 Pages) TI

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AM3894

AM3892

SPRS681A – OCTOBER 2010 – REVISED MARCH 2011

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For the internal pullup/pulldown resistors for all device pins, see the peripheral/system-specific terminal

functions tables in Section 3.2.

4.3

Boot Sequence

The boot sequence is a process by which the device's memory is loaded with program and data sections,

and by which some of the device's internal registers are programmed with predetermined values. The boot

sequence is started automatically after each device-level global reset. For more details on device-level

global resets, see Section 7.2. There are several methods by which the memory and register initialization

can take place. Each of these methods is referred to as a boot mode. The boot mode to be used is

selected at reset. The device is booted through multiple means—primary bootloaders within internal ROM

or EMIF4, and secondary user bootloaders from peripherals or external memories. The maximum size of

the boot image is 255KB (ROM uses 1KB internally). Boot modes, pin configurations, and register

configurations required for booting the device, are described in the following subsections.

The following boot modes are supported:

•

NOR Flash boot (muxed and non-muxed, 8-bit or 16-bit)

•

NAND Flash boot (SLC and MLC with BCH ECC, 8-bit or 16-bit)

•

SPI boot (EEPROM or Flash, SPI mode 3, 24-bit)

•

SD boot (SD cards)

•

EMAC boot (TFTP client)

•

UART boot (X-modem client)

•

PCIe boot (client mode, PCIe 32 and PCIe 64).

The state of the device after boot is determined by sampling the input states of the BTMODE[4:0] pins

when device reset (POR or RESET) is deasserted. The sampled values are latched into the

CONTROL_STATUS register, which is part of the system configuration (SYSCFG) module.

The BTMODE [4:0] values determine the boot mode order according to Table 4-5. The first boot mode

listed for each BTMODE[4:0] configuration is executed as the primary boot mode. If the primary boot

mode fails, the second, third, and fourth boot modes are executed, in that order, until a successful boot is

completed.

Additional boot configuration pins determine the following system boot settings as shown in Table 3-1:

•

GPMC CS0 Default Bus Width

•

GPMC Wait Enable

•

GPMC Address/Data Multiplexing.

The GPMC CS0 default operation is determined by the CS0BW, CS0WAIT, and CS0MUX[1:0] inputs.

For more detailed information on booting the device, see the AM38x Sitara ARM Microprocessors (MPUs)

Technical Reference Manual (literature number SPRUGX7).

106

Device Configurations

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