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AM3892 Datasheet(PDF) 107 Page - Texas Instruments |
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AM3892 Datasheet(HTML) 107 Page - Texas Instruments |
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107 / 299 page  AM3894 AM3892 www.ti.com SPRS681A – OCTOBER 2010 – REVISED MARCH 2011 Table 4-5. Boot Mode Order BTMODE[4] = 1 BTMODE[4] = 0 MEMORY BOOTING PREFERRED PERIPHERAL BOOTING PREFERRED BTMODE[3:0] FIRST SECOND THIRD FOURTH FIRST SECOND THIRD FOURTH XIP(1) UART EMAC SD RESERVED RESERVED RESERVED RESERVED 0000 XIPWAIT(1) UART EMAC SD UART XIPWAIT(1) SD SPI 0001 NAND NANDI2C SPI UART UART SPI NAND NANDI2C 0010 NAND NANDI2C SD UART UART SPI XIP(1) SD 0011 NAND NANDI2C SPI EMAC EMAC SPI NAND NANDI2C 0100 NANDI2C SD EMAC UART RESERVED RESERVED RESERVED RESERVED 0101 SPI SD UART EMAC RESERVED RESERVED RESERVED RESERVED 0110 SD SPI UART EMAC EMAC SD SPI XIP(1) 0111 SPI SD PCIE_32 RESERVED PCIE_32 RESERVED RESERVED RESERVED 1000 SPI SD PCIE_64 RESERVED PCIE_64 RESERVED RESERVED RESERVED 1001 RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED 1010 RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED 1011 RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED 1100 RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED 1101 RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED 1110 GP Fast EMAC UART PCIE_32 GP Fast UART EMAC PCIE_64 1111 External Boot External Boot (1) GPMC CS0 eXecute In Place (XIP) and eXecute In Place with Wait Monitoring (XIPWAIT) boot for NOR/OneNAND/ROM. For details, see the AM38x Sitara ARM Microprocessors (MPUs) Technical Reference Manual (literature number SPRUGX7). 4.3.1 Boot Mode Registers For details on the boot mode registers, see the AM38x Sitara ARM Microprocessors (MPUs) Technical Reference Manual (literature number SPRUGX7). Table 4-6. Device Boot Registers Summary HEX ADDRESS ACRONYM REGISTER NAME 0x4814 0040 CONTROL_STATUS Device Status 0x4814 0044 BOOTSTAT Device Boot Status 0x4814 0048 - 0x4814 007C - Reserved 4.4 Pin Multiplexing Control Device-level pin multiplexing is controlled on a pin-by-pin basis by the MUXMODE bits of the PINCTRL1 - PINCTRL321 registers in the SYSCFG module. The default state for each multiplexed pin is MUXMODE = 0x000. Pin multiplexing selects which of several peripheral pin functions control the pin's IO buffer output data values. The input from each pin is routed to all of the peripherals that share the pin, regardless of the MUXMODE setting. For details, see the table below and the MUXED column in the each of the Terminal Functions tables in Section 3.2. 4.4.1 PINCTRLx Register Descriptions Table 4-7. PINCTRLx Register Definition Bit Field Value Description 31:5 Reserved Reserved; Read returns 0 Copyright © 2010–2011, Texas Instruments Incorporated Device Configurations 107 Submit Documentation Feedback Product Folder Link(s): AM3894 AM3892 |
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