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AM3892 Datasheet(PDF) 182 Page - Texas Instruments

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Part # AM3892
Description  AM389x Sitara ARM Microprocessors (MPUs)
PDF  299 Pages
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Manufacturer  TI [Texas Instruments]
Direct Link  http://www.ti.com
Logo TI - Texas Instruments

AM3892 Datasheet(HTML) 182 Page - Texas Instruments

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AM3894
AM3892
SPRS681A – OCTOBER 2010 – REVISED MARCH 2011
www.ti.com
Table 8-25. Data Routing Specification(1)
NO.
PARAMETER
MIN
TYP
MAX
UNIT
1
DB0 nominal length(2)(3)
DQLM0
mils
2
DB1 nominal length(2)(4)
DQLM1
mils
3
DB2 nominal length(2)(5)
DQLM2
mils
4
DB3 nominal length(2)(6)
DQLM3
mils
5
DBn skew(7)
25
mils
6
DQSn+ to DQSn- skew
5
mils
7
DQSn to DBn skew(7)(8)
25
mils
8
Center-to-center DBn to other DDR3 trace spacing(9)(10)
4w
9
Center-to-center DBn to other DBn trace spacing(9)(11)
3w
10
DQSn center-to-center spacing(12)
11
DQSn center-to-center spacing to other net(9)
4w
(1)
External termination disallowed. Data termination should use built-in ODT functionality.
(2)
DQLMn is the longest Manhattan distance of a byte. For definition, see Section 8.3.2.16.2 and Figure 8-39.
(3)
DQLM0 is the longest Manhattan length for the net classes of Byte 0.
(4)
DQLM1 is the longest Manhattan length for the net classes of Byte 1.
(5)
DQLM2 is the longest Manhattan length for the net classes of Byte 2.
(6)
DQLM3 is the longest Manhattan length for the net slasses of Byte 3.
(7)
Length matching is only done within a byte. Length matching across bytes is neither required nor recommended.
(8)
Each DQS pair is length matched to its associated byte.
(9)
Center-to-center spacing is allowed to fall to minimum for up to 1250 mils of routed length.
(10) Other DDR3 trace spacing means other DDR3 net classes not within the byte.
(11) This applies to spacing within the net classes of a byte.
(12) DQS pair spacing is set to ensure proper differential impedance.
182
Peripheral Information and Timings
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