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AM3892 Datasheet(PDF) 185 Page - Texas Instruments |
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AM3892 Datasheet(HTML) 185 Page - Texas Instruments |
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185 / 299 page ![]() AM3894 AM3892 www.ti.com SPRS681A – OCTOBER 2010 – REVISED MARCH 2011 8.4.3.1 JTAG ID (JTAGID) Register Description Table 8-27. JTAG ID Register(1) HEX ADDRESS ACRONYM REGISTER NAME 0x4814 0600 JTAGID JTAG Identification Register(2) (1) IEEE Standard 1149.1-1990 Standard-Test-Access Port and Boundary Scan Architecture. (2) Read-only. Provides the device 32-bit JTAG ID. The JTAG ID register is a read-only register that identifies to the customer the JTAG/device ID. For this device, the JTAG ID register resides at address location 0x4814 0600. The register hex value for the device is: 0x0B81 E02F. For the actual register bit names and their associated bit field descriptions, see Figure 8-40 and Table 8-28. 31 28 27 12 11 1 0 VARIANT PART NUMBER (16-bit) MANUFACTURER (11-bit) LSB (4-bit) R-0000 R-1011 1000 0001 1110 R-0000 0010 111 R-1 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Figure 8-40. JTAG ID Register Description - Device Register Value: 0x0B81 E02F Table 8-28. JTAG ID Register Selection Bit Descriptions Bit Field Description 31:28 VARIANT Variant (4-bit) value. Device value: 0x0 27:12 PART NUMBER Part Number (16-bit) value. Device value: 0xB81E 11:1 MANUFACTURER Manufacturer (11-bit) value. Device value: 0x017 0 LSB LSB. This bit is read as a 1 for this device. 8.4.3.2 JTAG Electrical Data/Timing Table 8-29. Timing Requirements for IEEE 1149.1 JTAG (see Figure 8-41) NO. MIN MAX UNIT 1 tc(TCK) Cycle time, TCK 51.15 ns 1a tw(TCKH) Pulse duration, TCK high (40% of tc) 20.46 ns 1b tw(TCKL) Pulse duration, TCK low (40% of tc) 20.46 ns 3 tsu(TDI-TCK) Input setup time, TDI valid to TCK high (20% of (tc * 0.5)) 5.115 ns 3 tsu(TMS-TCK) Input setup time, TMS valid to TCK high (20% of (tc * 0.5)) 5.115 ns th(TCK-TDI) Input hold time, TDI valid from TCK high 10 ns 4 th(TCK-TMS) Input hold time, TMS valid from TCK high 10 ns Table 8-30. Switching Characteristics Over Recommended Operating Conditions for IEEE 1149.1 JTAG (see Figure 8-41) NO. PARAMETER MIN MAX UNIT 2 td(TCKL-TDOV) Delay time, TCK low to TDO valid 0 23.575(1) ns (1) (0.5 * tc) - 2 Copyright © 2010–2011, Texas Instruments Incorporated Peripheral Information and Timings 185 Submit Documentation Feedback Product Folder Link(s): AM3894 AM3892 |
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