CLRC663 datasheet(95/132 Pages) NXP

95 / 132 page

CLRC663

All information provided in this document is subject to legal disclaimers.

Product data sheet

COMPANY PUBLIC

Rev. 3.3 — 3 April 2012

171133

95 of 132

NXP Semiconductors

CLRC663

Contactless reader IC

9.12.5 Rcv

9.12.6 RxAna

This register allows to set the gain (rcv_gain) and high pass corner frequencies

(rcv_hpcf).

Table 160. RxThreshold bits

Bit

Symbol

Description

7 to 4

MinLevel

Defines the MinLevel of the reception.

Note: The MinLevel should be higher than the noise level in the system

3 to 0

MinLevelP

Defines the MinLevel of the phase shift detector unit

Table 161. Rcv register (address 38h)

Bit

Symbol

Rcv_Rx_single

RFU

SigInSel

RFU

CollLevel

Access

rights

r/w

Table 162. Rcv bits

Bit

Symbol

Description

Rcv_Rx_single

Single RXP Input Pin Mode;

0: Fully Differential;

1: Quasi-Differential

6RFU

5 to 4

SigInSel

Defines input for the signal processing unit

0h - idle

1h - internal analog block (RX)

2h - signal in over envelope (ISO/IEC14443A)

3h - signal in over s3c-generic

3 to 2

RFU

1 to 0

CollLevel

Defines the strength of a signal to be interpreted as a collision:

0h - Collision has at least 1/8 of signal strength

1h - Collision has at least 1/4 of signal strength

2h - Collision has at least 1/2 of signal strength

3h - Collision detection is switched off.

Table 163. RxAna register (address 39h)

Bit

Symbol

VMid_r_sel

RFU

rcv_hpcf

rcv_gain

Access

rights

r/w

CLRC663 Datasheet(PDF) 95 Page - NXP Semiconductors

CLRC663 Datasheet(HTML) 95 Page - NXP Semiconductors

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL