AMD-K6 datasheet(218/346 Pages) AMD

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System Management Mode (SMM)

Chapter 10

AMD-K6® Processor Data Sheet

20695H/0—March 1998

Preliminary Information

Upon entry into SMM, the halt restart slot is defined as follows:

Bits 15–1—Reserved

Bit 0—Point of entry to SMM:

1 = entered from Halt state

0 = not entered from Halt state

After entry into the SMI handler and before returning from

SMM, the halt restart slot can be written using the following

definition:

Bits 15–1—Reserved

Bit 0—Point of return when exiting from SMM:

1 = return to Halt state

0 = return to next instruction after the HLT instruction

If the return from SMM takes the processor back to the Halt

state, the HLT instruction is not re-executed, but the Halt

special bus cycle is driven on the bus after the return.

10.7

I/O Trap Dword

If the assertion of SMI# is recognized during the execution of an

I/O instruction, the I/O trap dword at offset FFA4h in the SMM

state-save area contains information about the instruction. The

fields of the I/O trap dword are configured as follows:

Bits 31–16—I/O port address

Bits 15–4—Reserved

Bit 3—REP (repeat) string operation (1 = REP string, 0 = not

a REP string)

Bit 2—I/O string operation (1 = I/O string, 0 = not an I/O

string)

Bit 1—Valid I/O instruction (1 = valid, 0 = invalid)

Bit 0—Input or output instruction (1 = INx, 0 = OUTx)

Table 36 shows the format of the I/O trap dword.

Table 36. I/O Trap Dword Configuration

31—16

15—4

I/O Port

Address

Reserved

REP String

Operation

I/O String

Operation

Valid I/O

Instruction

Input or

Output

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