AMD-K6 datasheet(222/346 Pages) AMD

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Test and Debug

Chapter 11

AMD-K6® Processor Data Sheet

20695H/0—March 1998

Preliminary Information

11.2

Tri-State Test Mode

The Tri-State Test mode causes the processor to float its output

and bidirectional pins, which is useful for board-level

manufa cturing testi ng. In thi s mode, th e processo r i s

electrically isolated from other components on a system board,

allowing automated test equipment (ATE) to test components

that drive the same signals as those the processor floats.

If the FLUSH# signal is sampled Low during the falling

transition of RESET, the processor enters the Tri-State Test

mode. (See “FLUSH# (Cache Flush)” on page 97 for the

specific sampling requirements.) The signals floated in the

Tri-State Test mode are as follows:

The VCC2DET and TDO signals are the only outputs not

floated in the Tri-State Test mode. VCC2DET must remain Low

to ensure the system continues to supply the specified

processor core voltage to the VCC2 pins. TDO is never floated

because the Boundary-Scan Test Access Port must remain

enabled at all times, including during the Tri-State Test mode.

The Tri-State Test mode is exited when the processor samples

RESET asserted.

A[31:3]

D/C#

M/IO#

ADS#

D[63:0]

PCD

ADSC#

DP[7:0]

PCHK#

FERR#

PWT

APCHK#

HIT#

SCYC

BE[7:0]#

HITM#

SMIACT#

BREQ

HLDA

W/R#

CACHE#

LOCK#

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