AMD-K6 datasheet(264/346 Pages) AMD

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246

Signal Switching Characteristics

Chapter 16

AMD-K6® Processor Data Sheet

20695H/0—March 1998

Preliminary Information

16.6

Input Setup and Hold Timings for 66-MHz Bus Operation

Table 50. Input Setup and Hold Timings for 66-MHz Bus Operation

Symbol

Parameter Description

Preliminary Data

Figure

Comments

Min

Max

t44

A[31:5] Setup Time

6.0 ns

t45

A[31:5] Hold Time

1.0 ns

t46

A20M# Setup Time

5.0 ns

Note 1

t47

A20M# Hold Time

1.0 ns

Note 1

t48

AHOLD Setup Time

5.5 ns

t49

AHOLD Hold Time

1.0 ns

t50

AP Setup Time

5.0 ns

t51

AP Hold Time

1.0 ns

t52

BOFF# Setup Time

5.5 ns

t53

BOFF# Hold Time

1.0 ns

t54

BRDY# Setup Time

5.0 ns

t55

BRDY# Hold Time

1.0 ns

t56

BRDYC# Setup Time

5.0 ns

t57

BRDYC# Hold Time

1.0 ns

t58

D[63:0] Read Data Setup Time

2.8 ns

t59

D[63:0] Read Data Hold Time

1.5 ns

t60

DP[7:0] Read Data Setup Time

2.8 ns

t61

DP[7:0] Read Data Hold Time

1.5 ns

t62

EADS# Setup Time

5.0 ns

t63

EADS# Hold Time

1.0 ns

t64

EWBE# Setup Time

5.0 ns

t65

EWBE# Hold Time

1.0 ns

t66

FLUSH# Setup Time

5.0 ns

Note 2

t67

FLUSH# Hold Time

1.0 ns

Note 2

Notes:

1. These level-sensitive signals can be asserted synchronously or asynchronously. To be sampled on a specific clock edge, setup and

hold times must be met. If asserted asynchronously, they must be asserted for a minimum pulse width of two clocks.

2. These edge-sensitive signals can be asserted synchronously or asynchronously. To be sampled on a specific clock edge, setup and

hold times must be met. If asserted asynchronously, they must have been negated at least two clocks prior to assertion and must

remain asserted at least two clocks.

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