AMD-K6 datasheet(269/346 Pages) AMD

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Chapter 16

Signal Switching Characteristics

251

20695H/0—March 1998

AMD-K6® Processor Data Sheet

Preliminary Information

t68

HOLD Setup Time

5.0 ns

t69

HOLD Hold Time

1.5 ns

t70

IGNNE# Setup Time

5.0 ns

Note 1

t71

IGNNE# Hold Time

1.0 ns

Note 1

t72

INIT Setup Time

5.0 ns

Note 2

t73

INIT Hold Time

1.0 ns

Note 2

t74

INTR Setup Time

5.0 ns

Note 1

t75

INTR Hold Time

1.0 ns

Note 1

t76

INV Setup Time

5.0 ns

t77

INV Hold Time

1.0 ns

t78

KEN# Setup Time

5.0 ns

t79

KEN# Hold Time

1.0 ns

t80

NA# Setup Time

4.5 ns

t81

NA# Hold Time

1.0 ns

t82

NMI Setup Time

5.0 ns

Note 2

t83

NMI Hold Time

1.0 ns

Note 2

t84

SMI# Setup Time

5.0 ns

Note 2

t85

SMI# Hold Time

1.0 ns

Note 2

t86

STPCLK# Setup Time

5.0 ns

Note 1

t87

STPCLK# Hold Time

1.0 ns

Note 1

t88

WB/WT# Setup Time

4.5 ns

t89

WB/WT# Hold Time

1.0 ns

Table 52. Input Setup and Hold Timings for 60-MHz Bus Operation (continued)

Symbol

Parameter Description

Preliminary Data

Figure

Comments

Min

Max

Notes:

1. These level-sensitive signals can be asserted synchronously or asynchronously. To be sampled on a specific clock edge, setup and

hold times must be met. If asserted asynchronously, they must be asserted for a minimum pulse width of two clocks.

2. These edge-sensitive signals can be asserted synchronously or asynchronously. To be sampled on a specific clock edge, setup and

hold times must be met. If asserted asynchronously, they must have been negated at least two clocks prior to assertion and must

remain asserted at least two clocks.

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