AMD-K6 datasheet(270/346 Pages) AMD

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252

Signal Switching Characteristics

Chapter 16

AMD-K6® Processor Data Sheet

20695H/0—March 1998

Preliminary Information

16.9

RESET and Test Signal Timing

Table 53. RESET and Configuration Signals (60-MHz and 66-MHz Operation)

Symbol

Parameter Description

Preliminary Data

Figure

Comments

Min

Max

t90

RESET Setup Time

5.0 ns

t91

RESET Hold Time

1.0 ns

t92

RESET Pulse Width, VCC and CLK Stable

15 clocks

t93

RESET Active After VCC and CLK Stable

1.0 ms

t94

BF[2:0] Setup Time

1.0 ms

Note 3

t95

BF[2:0] Hold Time

2 clocks

Note 3

t96

BRDYC# Hold Time

1.0 ns

Note 4

t97

BRDYC# Setup Time

2 clocks

Note 2

t98

BRDYC# Hold Time

2 clocks

Note 2

t99

FLUSH# Setup Time

5.0 ns

Note 1

t100

FLUSH# Hold Time

1.0 ns

Note 1

t101

FLUSH# Setup Time

2 clocks

Note 2

t102

FLUSH# Hold Time

2 clocks

Note 2

Notes:

1. To be sampled on a specific clock edge, setup and hold times must be met the clock edge before the clock edge on which RESET

is sampled negated.

2. If asserted asynchronously, these signals must meet a minimum setup and hold time of two clocks relative to the negation of

RESET.

3. BF[2:0] must meet a minimum setup time of 1.0 ms and a minimum hold time of two clocks relative to the negation of RESET.

4. If RESET is driven synchronously, BRDYC# must meet the specified hold time relative to the negation of RESET.

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