AMD-K6 datasheet(301/346 Pages) AMD

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Chapter 24

Software Environment

283

20695H/0—March 1998

AMD-K6® Processor Data Sheet

Preliminary Information

Figure 103. SYSCALL/SYSRET Target Address Register (STAR)

24.2

Instructions Supported by the AMD-K6® Processor

This section documents the x86 instructions supported by the

AMD-K6 processor Model 7 that are not supported by AMD-K6

processor Model 6. For information about the remaining x86

instructions supported by the AMD-K6 processor Model 6, see

Chapter 3, “Software Environment” on page 21.

Table 62 shows the instruction mnemonic, opcode, modR/M

by te, dec o de typ e , and R I SC 86 op erat ion( s) fo r each

instruction. The first column of the tables indicates the

instruction mnemonic and operand types. The second and third

columns list all applicable opcode bytes. The fourth column

lists the modR/M byte when used by the instruction. The

modR/M byte defines the instruction as a register or memory

form. The fifth column lists the type of instruction decode —

short, long, and vector. The sixth column lists the type of

RISC86 operation(s) required for the instruction.

Target EIP Address

SYSCALL CS Selector and SS

Selector Base

SYSRET CS Selector and SS

Selector Base

Table 61. SYSCALL/SYSRET Target Address Register (STAR) Definition

Bit

Description

R/W

63–48

SYSRET CS and SS Selector Base

R/W

47–32

SYSCALL CS and SS Selector Base

R/W

31–0

Target EIP Address

R/W

Table 62. Integer Instructions

Instruction Mnemonic

First

Byte

Second

Byte

ModR/M

Byte

Decode

Type

RISC86®

Opcodes

SYSCALL

0Fh

05h

vector

SYSRET

0Fh

07h

vector

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