DP83620 datasheet(34/105 Pages) TI

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DP83620

SNLS339C – JANUARY 2011 – REVISED APRIL 2013

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5.3

AUTO-MDIX

When enabled, this function utilizes Auto-Negotiation to determine the proper configuration for

transmission and reception of data and subsequently selects the appropriate MDI pair for MDI/MDIX

operation. The function uses a random seed to control switching of the crossover circuitry. This

implementation

complies

with

the

corresponding

IEEE

802.3

Auto-Negotiation

and

Crossover

Specifications.

Auto-MDIX is enabled by default and can be configured via PHYCR (19h) register, bits [15:14].

Neither Auto-Negotiation nor Auto-MDIX is required to be enabled in forcing crossover of the MDI pairs.

Forced crossover can be achieved through the FORCE_MDIX bit, bit 14 of PHYCR (19h) register.

5.4

AUTO-CROSSOVER IN FORCED MODE

When enabled, this function operates in a manner similar to Auto-MDIX. If no link activity is seen,

switching of the crossover circuitry is based on a random seed. Valid link activity can be link pulses (Auto-

Negotiation link pulse or 10M link pulses) or 100M signaling. Once valid link activity is seen, crossover will

stop to allow the receive and link functions will proceed normally.

Auto-crossover in forced mode allows for shorter link times because it does not require potentially lengthy

Auto-Negotiation transactions prior to link establishment. Link establishment via Auto-crossover can be

accomplished in full or half duplex configuration, but both sides of the link must be forced to the same

duplex configuration.

Auto-crossover in forced mode is disabled by default and must be configured via PCSR (16h) register, bit

15.

Forced crossover can be achieved while Auto-crossover is enabled through the FORCE_MDIX bit, bit 14

of PHYCR (19h) register.

NOTE: Auto-MDIX and Auto-crossover in forced mode are mutually exclusive and should not be enabled

concurrently. Prior to enabling Auto-crossover in forced mode, Auto-Negotiation and Auto-MDIX should be

disabled.

5.5

PHY ADDRESS

The five PHY address strapping pins are shared with the RXD[3:0] pins and COL pin as shown below.

Table 5-2. PHY Address Mapping

Pin #

PHYAD Function

RXD Function

PHYAD0

COL

PHYAD1

RXD_3

PHYAD2

RXD_2

PHYAD3

RXD_1

PHYAD4

RXD_0

The DP83620 can be set to respond to any of 32 possible PHY addresses via strap pins. The information

is latched into the PHYCR register (address 19h, bits [4:0]) at device power-up and hardware reset. Each

DP83620 or port sharing an MDIO bus in a system must have a unique physical address.

The DP83620 supports PHY Address strapping values 0 (<00000>) through 31 (<11111>). Strapping

PHY Address 0 puts the part into Isolate Mode. It should also be noted that selecting PHY Address 0

via an MDIO write to PHYCR will not put the device in Isolate Mode. See MII Isolate Mode for more

information.

For further detail relating to the latch-in timing requirements of the PHY Address pins, as well as the other

hardware configuration pins, refer to the Reset summary in Reset Operation.

Configuration

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