DP83620 datasheet(77/105 Pages) TI

77 / 105 page

DP83620

www.ti.com

SNLS339C – JANUARY 2011 – REVISED APRIL 2013

Table 10-12. PHY Status Register (PHYSTS), address 0x10 (continued)

Bit

Bit Name

Default

Description

RECEIVE ERROR

0, RO/LH

Receive Error Latch:

LATCH

This bit will be cleared upon a read of the RECR register.

1 = Receive error event has occurred since last read of RXERCNT (address

15h, Page 0).

0 = No receive error event has occurred.

POLARITY STATUS

0, RO

Polarity Status:

This bit is a duplication of bit 4 in the 10BTSCR register. This bit will be cleared

upon a read of the 10BTSCR register, but not upon a read of the PHYSTS

1 = Inverted Polarity detected.

0 = Correct Polarity detected.

FALSE CARRIER SENSE

0, RO/LH

False Carrier Sense Latch:

LATCH

This bit will be cleared upon a read of the FCSR register.

1 = False Carrier event has occurred since last read of FCSCR (address 14h).

0 = No False Carrier event has occurred.

SIGNAL DETECT

0, RO/LL

100Base-TX qualified Signal Detect from PMA:

This is the SD that goes into the link monitor. It is the AND of raw SD and

descrambler lock, when address 16h, bit 8 (page 0) is set. When bit 8 of

address 16h is cleared, it will be equivalent to the raw SD from the PMD.

DESCRAMBLER LOCK

0, RO/LL

100Base-TX Descrambler Lock from PMD.

PAGE RECEIVED

0, RO

Link Code Word Page Received:

This is a duplicate of the Page Received bit in the ANER register, but this bit

will not be cleared upon a read of the PHYSTS register.

1 = A new Link Code Word Page has been received. Cleared on read of the

ANER (address 06h, bit 1).

0 = Link Code Word Page has not been received.

MII INTERRUPT

0, RO

MII Interrupt Pending:

1 = Indicates that an internal interrupt is pending. Interrupt source can be

determined by reading the MISR Register (12h). Reading the MISR will clear

the Interrupt.

0 = No interrupt pending.

REMOTE FAULT

0, RO

Remote Fault:

1 = Remote Fault condition detected (cleared on read of BMSR (address 01h)

Fault via Auto-Negotiation.

0 = No remote fault condition detected.

JABBER DETECT

0, RO

Jabber Detect: This bit only has meaning in 10 Mb/s mode.

This bit is a duplicate of the Jabber Detect bit in the BMSR register, except that

it is not cleared upon a read of the PHYSTS register.

1 = Jabber condition detected.

0 = No Jabber.

AUTO-NEG COMPLETE

0, RO

Auto-Negotiation Complete:

1 = Auto-Negotiation complete.

0 = Auto-Negotiation not complete.

LOOPBACK STATUS

0, RO

Loopback:

1 = Loopback enabled.

0 = Normal operation.

Submit Documentation Feedback

Product Folder Links: DP83620

DP83620 Datasheet(PDF) 77 Page - Texas Instruments

DP83620 Datasheet(HTML) 77 Page - Texas Instruments

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL