DP83620 datasheet(99/105 Pages) TI

99 / 105 page

DP83620

www.ti.com

SNLS339C – JANUARY 2011 – REVISED APRIL 2013

10.5 PHY STATUS FRAME CONFIGURATION REGISTER - PAGE 5

The Page 5 PHY Status Frame Configuration Register is accessible by setting bits [2:0] = 101 of

PAGESEL (13h).

10.5.1 PHY Status Frame Configuration Register(PSF_CFG), Page 5

This register provides configuration for the PHY Status Frame function.

Table 10-39. PHY Status Frame Configuration Register(PSF_CFG), address 0x18

Bit

Bit Name

Default

Description

15:13

RESERVED

000, RO

Reserved: Writes ignored, Read as 0

12:11

MAC_SRC_ADD

00, RW

PHY Status Frame Mac Source Address:

Selects source address as follows:

00 : Use Mac Address [08 00 17 0B 6B 0F]

01 : Use Mac Address [08 00 17 00 00 00]

10 : Use Mac Multicast Dest Address

11 : Use Mac Address [00 00 00 00 00 00]

10:8

MIN_PRE

000, RW

PHY Status Frame Minimum Preamble:

Determines the minimum preamble bytes required for sending packets on the MII

interface. It is recommended that this be set to the smallest value the MAC will

tolerate.

PSF_ENDIAN

0, RW

PHY Status Frame Endian Control:

For each 16-bit field in a Status Message, the data will normally be presented in

network byte order (Most significant byte first). If this bit is set to a 1, the byte data

fields will be reversed so that the least significant byte is first.

PSF_IPV4

0, RW

PHY Status Frame IPv4 Enable:

This bit controls the type of packet used for PHY Status Frames.

0 = Layer2 Ethernet packets

1 = IPv4 packets.

PSF_PCF_RD

0, RW

PHY Control Frame Read PHY Status Frame Enable:

Enable PHY Status Frame delivery of PHY Control Frame read data. Data read via

a PHY Control Frame will be returned in a PHY Status Frame.

PSF_ERR_EN

0, RW

PSF Error PHY Status Frame Enable:

Enable PHY Status Frame delivery of PHY Status Frame Errors. This bit will not

independently enable PHY Status Frame operation. One of the other enable bits

must be set for PHY Status Frames to be generated.

3:0

RESERVED

0000, RW

Reserved: Must be 0x0.

Submit Documentation Feedback

Product Folder Links: DP83620

DP83620 Datasheet(PDF) 99 Page - Texas Instruments

DP83620 Datasheet(HTML) 99 Page - Texas Instruments

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL