DP83620 datasheet(98/105 Pages) TI

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DP83620

SNLS339C – JANUARY 2011 – REVISED APRIL 2013

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Table 10-37. Link Quality Data Register (LQDR), address 0x1E (continued)

Bit

Bit Name

Default

Description

LQ_THR_SEL

0, RW

Link Quality Threshold Select:

This bit selects the Link Quality Threshold to be read or written. A 0 selects the

Low threshold, while a 1 selects the high threshold. When combined with the

LQ_PARAM_SEL field, the following encodings are available {LQ_PARAM_SEL,

LQ_THR_SEL}:

000,0: DEQ_C1 Low

000,1: DEQ_C1 High

001,0: DAGC Low

001,1: DAGC High

010,0: DBLW Low

010,1: DBLW High

011,0: Frequency Offset Low

011,1: Frequency Offset High

100,0: Frequency Control Low

100,1: Frequency Control High

101,0: Variance High bits 7:0 (Variance bits 23:16)

101,1: Variance High bits 15:8 (Variance bits 31:24)

7:0

LQ_THR_DATA

1000 0000, RW

Link Quality Threshold Data:

The operation of this field is dependent on the value of the SAMPLE_PARAM bit.

If SAMPLE_PARAM = 0:

On a write, this value contains the data to be written to the selected Link Quality

Threshold register.

On a read, this value contains the current data in the selected Link Quality

Threshold register.

If SAMPLE_PARAM = 1:

On a read, this value contains the sampled parameter value. This value will

remain unchanged until a new read sequence is started.

10.4.11 Link Quality Monitor Register 2 (LQMR2), Page 2

This register contains additional controls for the Link Quality Monitor function. The Link Quality Monitor

provides a mechanism for programming a set of thresholds for DSP parameters. If the thresholds are

violated, an interrupt will be asserted if enabled in the MISR. Monitor control and status are available in

this register, while the LQDR register controls read/write access to threshold values and current parameter

values. Reading of LQMR2 register clears its warning bits but does NOT re-arm the interrupt generation;

LQMR must be read to re-arm interrupt generation. In addition, this register provides a mechanism for

allowing automatic reset of the 100 Mb link based on the Link Quality Monitor variance status.

Table 10-38. Link Quality Monitor Register 2 (LQMR2), address 0x1F

Bit

Bit Name

Default

Description

15:11

RESERVED

0000 0, RO

Reserved: Writes ignored, Read as 0

RESTART_ON_VAR

0, RW

Restart on Variance Warning:

Allow automatic reset of DSP and restart of 100 Mb Adaption on detecting a

Frequency Offset Threshold violation. If the SD_Option bit, PCSR[8], is set to 0, the

threshold violation will also result in a drop in Link status.

9:2

RESERVED

00 0000 00, RO

Reserved: Writes ignored, Read as 0

VAR_HI_WARN

0, RO/COR

Variance High Warning:

This bit indicates the Variance High Threshold was exceeded. This register bit will

be cleared on read.

RESERVED

0, RO

Reserved: Writes ignored, Read as 0

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