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DP83620 Datasheet(PDF) 68 Page - Texas Instruments |
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DP83620 Datasheet(HTML) 68 Page - Texas Instruments |
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68 / 105 page  DP83620 SNLS339C – JANUARY 2011 – REVISED APRIL 2013 www.ti.com Table 10-2. Register Table (continued) Register Name Addr Tag Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 LED Direct Control 18h LEDCR Reserved Reserved Reserved Reserved DIS_SPDL DIS_LNKL DIS_ACTL LEDACT_R BLINK_FR BLINK_FR DRV_SPDLE DRV_LNKL DRV_ACTLE SPDLED LNKLED ACTLED Register ED ED ED X EQ EQ D ED D PHY Control 19h PHYCR MDIX_EN FORCE_M PAUSE_R PAUSE_TX BIST_FE PSR_15 BIST_ BIST_STA BP_STRET LED_ LED_ PHY PHY PHY PHY PHY Register DIX X RT CH STATUS CNFG[1] CNFG[0] ADDR ADDR ADDR ADDR ADDR 10Base-T 1Ah 10BTSCR Reserved Reserved Reserved Reserved SQUELCH SQUELCH SQUELCH LOOPBAC LP_DIS FORCE_ FORCE_POL POLARITY AUTOPOL_DI 10BT_SCA HEARTBEAT JABBER_D Status/Control K_10_DIS COR S LE_MSB _DIS IS LINK_10 Register CD Test Control 1Bh CDCTRL1 BIST_ERR BIST_ERR BIST_ERR BIST_ERR BIST_ERR BIST_ERR BIST_ERR BIST_ERR Reserved MII_CLOC BIST_CONT CDPATTE MDIO_PULL_ PATT_GAP CDPATTSEL CDPATTS and BIST OR_COUN OR_COUN OR_COUN OR_COUN OR_COUN OR_COUN OR_COUN OR_COUN K_EN N_10 EN _10M EL Extensions T T T T T T T T Register PHY Control 1Ch PHYCR2 Reserved Reserved SYNC_EN CLK_OUT BC_WRITE PHYTER_ SOFT_RE Reserved Reserved Reserved Reserved Reserved Reserved Reserved CLK_OUT_DI Reserved Register 2 ET_EN RXCLK COMP SET S Energy Detect 1Dh EDCR ED_EN ED_AUTO ED_AUTO ED_MAN ED_BURS ED_PWR_ ED_ERR_ ED_DATA_ ED_ERR_ ED_ERR_ ED_ERR_CO ED_ERR_ ED_DATA_C ED_DATA_ ED_DATA_C ED_DATA_ Control Register _UP _DOWN T_DIS STATE MET MET COUNT COUNT UNT COUNT OUNT COUNT OUNT COUNT RESERVED 1Eh Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved PHY Control 1Fh PCFCR PCF_STS_ PCF_STS_ Reserved Reserved Reserved Reserved Reserved PCF_DA_S PCF_INT_ PCF_INT_ PCF_BC_DIS PCF_BUF PCF_BUF PCF_BUF PCF_BUF PCF_EN Frames ERR OK EL CTL CTL Configuration Register TEST REGISTERS - PAGE 1 RESERVED 14h-1Dh Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Signal Detect 1Eh SD_CNFG Reserved Reserved Reserved Reserved Reserved Reserved Reserved SD_Time Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Configuration Register RESERVED 1Fh Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved LINK DIAGNOSTICS REGISTERS - PAGE 2 100 Mb Length 14h LEN100_D Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved CABLE_LE CABLE_LE CABLE_LEN CABLE_LE CABLE_LEN CABLE_LE CABLE_LEN CABLE_LE Detect Register ET N N N N N 100 Mb Frequency 15h FREQ100 SAMPLE_F Reserved Reserved Reserved Reserved Reserved Reserved SEL_FC FREQ_OF FREQ_OF FREQ_OFFS FREQ_OF FREQ_OFFS FREQ_OF FREQ_OFFS FREQ_OF Offset Indication REQ FSET FSET ET FSET ET FSET ET FSET Register TDR Control 16h TDR_CTRL TDR_ENA TDR_100M TX_CHAN RX_CHAN SEND_TD TDR_WIDT TDR_WIDT TDR_WIDT TDR_MIN_ Reserved RX_THRESH RX_THRE RX_THRESH RX_THRE RX_THRESH RX_THRE Register BLE b NEL NEL R H H H MODE OLD SHOLD OLD SHOLD OLD SHOLD TDR Window 17h TDR_WIN TDR_STA TDR_STA TDR_STA TDR_STA TDR_STA TDR_STA TDR_STA TDR_STA TDR_STO TDR_STO TDR_STOP TDR_STO TDR_STOP TDR_STO TDR_STOP TDR_STO Register RT RT RT RT RT RT RT RT P P P P P TDR Peak 18h TDR_PEA Reserved Reserved TDR_PEA TDR_PEA TDR_PEA TDR_PEA TDR_PEA TDR_PEA TDR_PEA TDR_PEA TDR_PEAK_ TDR_PEA TDR_PEAK_ TDR_PEA TDR_PEAK_ TDR_PEA Measurement K K K K K K K K_TIME K_TIME TIME K_TIME TIME K_TIME TIME K_TIME Register TDR Threshold 19h TDR_THR Reserved Reserved Reserved Reserved Reserved Reserved Reserved TDR_THR_ TDR- TDR- TDR- TDR- TDR- TDR- TDR- TDR- Measurement MET THR_TIME THR_TIME THR_TIME THR_TIME THR_TIME THR_TIME THR_TIME THR_TIME Register Variance Control 1Ah VAR_CTRL VAR_RDY Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved LOAD_VAR_ LOAD_VA VAR_FREEZ VAR_TIME VAR_TIMER VAR_ENA Register HI R_LO E R BLE Variance Data 1Bh VAR_DAT VAR_DAT VAR_DAT VAR_DAT VAR_DAT VAR_DAT VAR_DAT VAR_DAT VAR_DAT VAR_DAT VAR_DAT VAR_DATA VAR_DAT VAR_DATA VAR_DAT VAR_DATA VAR_DAT Register A A A A A A A A A A A A A A Reserved 1Ch Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Link Quality 1Dh LQMR LQM_ENA RESTART_ RESTART_ RESTART_ RESTART_ RESTART_ FC_HI_WA FC_LO_W FREQ_HI_ FREQ_LO_ DBLW_HI_W DBLW_LO DAGC_HI_W DAGC_LO C1_HI_WAR C1_LO_W Monitor Register BLE ON_FC ON_FREQ ON_DBLW ON_DAGC ON_C1 RN ARN WARN WARN ARN _WARN ARN _WARN N ARN 68 Register Block Copyright © 2011–2013, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: DP83620 |
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