DP83620 datasheet(45/105 Pages) TI

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DP83620

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SNLS339C – JANUARY 2011 – REVISED APRIL 2013

When heartbeat is enabled (only applicable to 10 Mb/s operation), approximately 1µs after the

transmission of each packet, a Signal Quality Error (SQE) signal of approximately 10 bit times is

generated (internally) to indicate successful transmission. SQE is reported as a pulse on the COL signal of

the MII.

Collision is not indicated during Full Duplex operation.

6.1.3

Carrier Sense

In 10 Mb/s operation, Carrier Sense (CRS) is asserted due to receive activity once valid data is detected

via the Smart Squelch function. During 100 Mb/s operation CRS is asserted when a valid link (SD) and

two non-contiguous zeros are detected on the line.

For 10 or 100 Mb/s Half Duplex operation, CRS is asserted during either packet transmission or reception.

For 10 or 100 Mb/s Full Duplex operation, CRS is asserted only due to receive activity.

CRS is deasserted following an end of packet.

6.2

REDUCED MII INTERFACE

The DP83620 incorporates the Reduced Media Independent Interface (RMII) as specified in the RMII

specification (rev 1.2) from the RMII Consortium. This interface may be used to connect PHY devices to a

MAC in 10/100 Mb/s systems using a reduced number of pins. In this mode, data is transferred 2-bits at a

time using the 50 MHz RMII_REF clock for both transmit and receive. The following pins are used in RMII

mode:

— TX_EN

— TXD[1:0]

— RX_ER (optional for MAC)

— CRS/CRS_DV

— RXD[1:0]

— X1 (25 MHz in RMII Master mode, 50 MHz in RMII Slave mode)

— RX_CLK, TX_CLK, CLK_OUT (50 MHz RMII reference clock in RMII Master mode only)

In addition, the RMII mode supplies an RX_DV signal which allows for a simpler method of recovering

receive data without having to separate RX_DV from the CRS_DV indication. This is especially useful for

systems which do not require CRS, such as systems that only support full-duplex operation. This signal is

also useful for diagnostic testing where it may be desirable to loop external Receive RMII data directly to

the transmitter.

The RX_ER output may be used by the MAC to detect error conditions. It is asserted for symbol errors

received during a packet, False Carrier events, and also for FIFO underrun or overrun conditions. Since

the PHY is required to corrupt receive data on an error, a MAC is not required to use RX_ER.

Since the reference clock operates at 10 times the data rate for 10 Mb/s operation, transmit data is

sampled every 10 clocks. Likewise, receive data will be generated every 10th clock so that an attached

device can sample the data every 10 clocks.

RMII Slave mode requires a 50 MHz oscillator to be connected to the device X1 pin. A 50 MHz crystal is

not supported. RMII Master mode can use either a 25 MHz oscillator connected to X1 or a 25 MHz crystal

connected to X1 and X2.

To tolerate potential frequency differences between the 50 MHz reference clock and the recovered receive

clock, the receive RMII function includes a programmable elasticity buffer. The elasticity buffer is

programmable to minimize propagation delay based on expected packet size and clock accuracy. This

allows for supporting a range of packet sizes including jumbo frames.

MAC Interface

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