DP83620 datasheet(63/105 Pages) TI

63 / 105 page

50:

130:

0.1 PF

Vdd

130:

All values are typical and are +/- 1%

PLACE RESISTORS AND

CAPACITORS CLOSE TO

THE DEVICE

PLACE RESISTORS

CLOSE TO THE FIBER

TRANSCEIVER

FXTDP

FXTDM

FXSD

FXRDP

FXRDM

80:

DP83620

www.ti.com

SNLS339C – JANUARY 2011 – REVISED APRIL 2013

9.2

FIBER NETWORK CIRCUIT

Figure 9-2 shows the recommended circuit for a 100 Mb/s fiber pair interface.

Figure 9-2. 100 Mb/s Fiber Pair Interface

9.3

ESD PROTECTION

Typically, ESD precautions are predominantly in effect when handling the devices or board before being

installed in a system. In those cases, strict handling procedures need be implemented during the

manufacturing process to greatly reduce the occurrences of catastrophic ESD events. After the system is

assembled, internal components are less sensitive from ESD events.

The network interface pins are more susceptible to ESD events.

9.4

CLOCK IN (X1) RECOMMENDATIONS

The DP83620 supports an external CMOS level oscillator source or a crystal resonator device.

Oscillator

If an external clock source is used, X1 should be tied to the clock source and X2 should be left floating.

The CMOS 25 MHz oscillator specifications for MII Mode are listed in Table 9-1. For RMII Slave Mode, the

CMOS 50 MHz oscillator specifications are listed in Table 9-2. For RMII Slave mode, it is not

recommended that the system clock out, Pin 24, be used as the reference clock to the MAC without first

verifying the interface timing. See SNLA076 for more details.

Design Guidelines

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