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DP83620 Datasheet(PDF) 26 Page - Texas Instruments |
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DP83620 Datasheet(HTML) 26 Page - Texas Instruments |
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26 / 105 page  Symbol T2.25.1 T2.25.3 T2.25.2 T2.25.4 RX_CLK TX_CLK CLK_OUT TXD[1:0] TX_EN PMD Output Pair Valid data DP83620 SNLS339C – JANUARY 2011 – REVISED APRIL 2013 www.ti.com 4.29 AC Specifications — Transmit Timing (Master Mode) Parameter Description Notes Min Typ Max Units T2.25.1 RX_CLK, TX_CLK, CLK_OUT Period 50 MHz Reference Clock 20 ns T2.25.2 TXD[1:0], TX_EN Data Setup to RX_CLK, 4 ns TX_CLK, CLK_OUT rising edge T2.25.3 TXD[1:0], TX_EN Data Hold from RX_CLK, 2 ns TX_CLK, CLK_OUT rising edge T2.25.4 RX_CLK, TX_CLK, CLK_OUT to PMD Output Pair From RX_CLK rising edge to 11 bits Latency(1) first bit of symbol (1) Latency measurement is made from the RX_CLK rising edge to the first bit of symbol. 26 Electrical Specifications Copyright © 2011–2013, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: DP83620 |
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