DP83620 datasheet(56/105 Pages) TI

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DP83620

SNLS339C – JANUARY 2011 – REVISED APRIL 2013

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7.2.3

Signal Detect

The signal detect function of the DP83620 is incorporated to meet the specifications mandated by the

ANSI FDDI TP-PMD Standard as well as the IEEE 802.3 100BASE-TX Standard for both voltage

thresholds and timing parameters.

Note that the reception of normal 10BASE-T link pulses and fast link pulses per IEEE 802.3u Auto-

Negotiation by the 100BASE-TX receiver do not cause the DP83620 to assert signal detect.

7.2.4

MLT-3 to Binary Decoder

The DP83620 decodes the MLT-3 information from the Digital Adaptive Equalizer block to binary NRZI

data.

7.2.5

Clock Recovery Module

The Clock Recovery function is implemented as a Phase detector and Loop Filter which accepts data and

error from the receive datapath to detect the phase of the recovered data. This phase information is fed

into the loop filter to determine an 8-bit signed frequency control. The 8-bit signed frequency control is

sent to the FCO in the Analog Front End to derive the receive clock. The extracted and synchronized

clock and data are used as required by the synchronous receive operations as generally depicted in

Figure 7-2.

7.2.6

NRZI to NRZ Decoder

In a typical application, the NRZI to NRZ decoder is required in order to present NRZ formatted data to the

descrambler (or to the code-group alignment block if the descrambler is bypassed).

7.2.7

Serial to Parallel

The 100BASE-TX receiver includes a Serial to Parallel converter which supplies 5-bit wide data symbols

to the PCS Rx state machine.

7.2.8

Descrambler

A serial descrambler is used to de-scramble the received NRZ data. The descrambler has to generate an

identical data scrambling sequence (N) in order to recover the original unscrambled data (UD) from the

scrambled data (SD) as represented in the equations:

Synchronization of the descrambler to the original scrambling sequence (N) is achieved based on the

knowledge that the incoming scrambled data stream consists of scrambled IDLE data. After the

descrambler has recognized 12 consecutive IDLE code-groups, where an unscrambled IDLE code-group

in 5B NRZ is equal to five consecutive ones (11111), it will synchronize to the receive data stream and

generate unscrambled data in the form of unaligned 5B code-groups.

In order to maintain synchronization, the descrambler must continuously monitor the validity of the

unscrambled data that it generates. To ensure this, a line state monitor and a hold timer are used to

constantly monitor the synchronization status. Upon synchronization of the descrambler, the hold timer

starts a 722 µs countdown. Upon detection of sufficient IDLE code-groups (58 bit times) within the 722 µs

period, the hold timer will reset and begin a new countdown. This monitoring operation will continue

indefinitely given a properly operating network connection with good signal integrity. If the line state

monitor does not recognize sufficient unscrambled IDLE code-groups within the 722 µs period, the entire

descrambler will be forced out of the current state of synchronization and reset in order to re-acquire

synchronization. The DP83604T also provides a bit (DESC_TIME, bit 7) in the PCSR register (0x16) that

increases the descrambler timeout from 722 µs to 2 ms to allow reception of packets up to 9kB in size

without losing descrambler lock.

Architecture

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