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DP83620 Datasheet(PDF) 91 Page - Texas Instruments |
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DP83620 Datasheet(HTML) 91 Page - Texas Instruments |
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91 / 105 page  DP83620 www.ti.com SNLS339C – JANUARY 2011 – REVISED APRIL 2013 10.3 TEST REGISTERS - PAGE 1 Page 1 Test Registers are accessible by setting bits [2:0] = 001 of PAGESEL (13h). 10.3.1 Signal Detect Configuration (SD_CNFG), Page 1 This register contains Signal Detect configuration control as well as some test controls to speed up Auto- neg testing. Table 10-27. Signal Detect Configuration (SD_CNFG), address 0x1E Bit Bit Name Default Description 15 RESERVED 1, RW RESERVED: Write as 1, read as 1. 14:1 RESERVED 000, RW RESERVED: Write as 0, read as 0. 2 11 RESERVED 0, RO RESERVED: Write ignored, read as 0. 10:9 RESERVED 00, RW RESERVED: Write as 0, read as 0. 8 SD_TIME 0, RW Signal Detect Time Setting this bit to a 1 enables a fast detection of loss of Signal Detect. This will result in a fast loss of Link indication. Approximate times to detect signal detect deassertion are: 1 = 1 µs 0 = 250 µs 7:0 RESERVED 0000 0000, RW RESERVED: Write as 0, read as 0. Copyright © 2011–2013, Texas Instruments Incorporated Register Block 91 Submit Documentation Feedback Product Folder Links: DP83620 |
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