DP83620 datasheet(30/105 Pages) TI

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T2.32.1

TX_CLK

Data

IDLE

Data

(J/K)

(TR)

T2.31.4

T2.31.1

T2.31.5

T2.31.3

T2.31.2

PMD Input

Pair

CRS/CSR_DV

RX_DV

RXD[3:0]

RX_ER

DP83620

SNLS339C – JANUARY 2011 – REVISED APRIL 2013

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4.35 AC Specifications — Single Clock MII (SCMII) Receive Timing

Parameter

Description

Notes

Min

Typ

Max

Units

T2.31.1

X1 Clock Period

25 MHz Reference Clock

T2.31.2

RXD[3:0], RX_DV and RX_ER output

From X1 rising edge

delay(1)

T2.31.3

100BASE-TX mode

CRS ON delay(2)(3)

bits

100BASE-FX mode

T2.31.4

100BASE-TX mode

CRS OFF delay(2)(4)

bits

100BASE-FX mode

T2.31.5

100BASE-TX mode

RXD[3:0] and RX_ER latency(5)

bits

100BASE-FX mode

(1)

Output delays assume a 25 pF load.

(2)

CRS is asserted and de-asserted asynchronously relative to the reference clock.

(3)

CRS ON delay is measured from the first bit of the JK symbol on the PMD Input Pair to assertion of CRS_DV.

(4)

CRS OFF delay is measured from the first bit of the TR symbol on the PMD Input Pair to de-assertion of CRS_DV.

(5)

Receive Latency is measured from the first bit of the symbol pair on the PMD Input Pair. Typical values are with the Elasticity Buffer set

to the default value (01).

4.36 AC Specifications — 100 Mb/s X1 to TX_CLK Timing

Parameter

Description

Notes

Min

Typ

Max

Units

T2.32.1

X1 to TX_CLK delay(1)

100 Mb/s Normal mode

(1)

X1 to TX_CLK timing is provided to support devices that use X1 instead of TX_CLK as the reference for transmit MII data.

Electrical Specifications

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