ICS1531 datasheet(31/76 Pages) ICST

31 / 76 page

Chapter 6

ICS1531 Rev N 12/1/99

December, 1999

ICS1531 Data Sheet - Preliminary

6.5.5

The DPA Offset (Dynamic Phase Adjust Offset) Register is used to select the clock edge offset.

Figure 6-2.

DPA Offset (As Determined by Regs 04 and 05)

Table 6-7.

DPA Offset Register

Bit

Bit Name

Bit Definition

Ac-

cess

Spec.

Func.

Re-

set

04:7-

04:6

Reserved

Reserved.

• See Section 6.1, “Reserved Bits”.

• These bits can be programmed to ‘0’.

––

04:5-

04:0

DPA_OS [5-0]

Dynamic Phase Adjust Offset [5-0].

As Figure 6-2 shows, these bits control the amount of offset

between the rising edge of the recovered HSYNC and the rising

edge of CLK.

• The offset is in discrete steps from 0 clock periods up to 1

clock period, minus one unit of a DPA delay.

• The unit of the DPA delay depends on both the pixel clock

output frequency and the number of delay element units (as

selected by Reg 05:1-0).

R/W

–

HSYNC

CLK Offset when

DPA_OS [5-0] = 0

One unit of

DPA Delay

tLow

One clock period

tHigh

CLK Offset when

DPA_OS [5-0] = 1

CLK Offset when

DPA_OS [5-0] = 2

CLK Offset when

DPA_OS [5-0] = Max

tHigh

Fixed delay

≈ 2.5 ns

1 unit of DPA delay

2 units of DPA delay

Maximum units of DPA delay

ICS1531 Datasheet(PDF) 31 Page - Integrated Circuit Systems

ICS1531 Datasheet(HTML) 31 Page - Integrated Circuit Systems

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76

Datasheet Download

Link URL