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ICS1531 Datasheet(PDF) 55 Page - Integrated Circuit Systems

Part # ICS1531
Description  Triple 8-bit MSPS A/D Converters with Line-Locked Clock Generator
PDF  76 Pages
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Manufacturer  ICST [Integrated Circuit Systems]
Direct Link  http://www.icst.com
Logo ICST - Integrated Circuit Systems

ICS1531 Datasheet(HTML) 55 Page - Integrated Circuit Systems

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Chapter 7
Programming
ICS1531 Rev N 12/1/99
December, 1999
55
Copyright © 1999, Integrated Circuit Systems, Inc.
All rights reserved.
ICS1531 Data Sheet - Preliminary
7.2
Programming Flow for Modifying PLL and DPA Settings
Figure 7-2.
ICS1531 Flow for Capture/Input Clock PLL
Set DPA Output
Delay to 0
Initialize
Registers 0 and 8
Set Input, PFD Gain, Post
Scaler, and Feedback Divider
Set DPA
Resolution
PLL Software Reset
DPA Software Reset
PLL
Locked
?
Change
PLL Freq.
?
Wait ~ 1ms
Wait ~ 1ms
Enable
Desired Outputs
Regs 0 through 3
Reg4[5:0]=0
Yes
Yes
No
No
RegA=0Ah
RegA=50h
Reg12[1]=1?
Done
Select Desired
DPA Output Delay
Reg4[5:0]
Reg6[6:2]



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