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ICS1531 Datasheet(PDF) 40 Page - Integrated Circuit Systems

Part # ICS1531
Description  Triple 8-bit MSPS A/D Converters with Line-Locked Clock Generator
PDF  76 Pages
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Manufacturer  ICST [Integrated Circuit Systems]
Direct Link  http://www.icst.com
Logo ICST - Integrated Circuit Systems

ICS1531 Datasheet(HTML) 40 Page - Integrated Circuit Systems

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ICS1531 Rev N 12/1/99
December, 1999
40
Chapter 6
Register Set
ICS1531 Data Sheet - Preliminary
Copyright © 1999, Integrated Circuit Systems, Inc.
All rights reserved.
6.5.21
Register 24h: PNLCLK-SSOE
The PNLCLK-SSOE (PNLCLK Spread-Spectrum Output Enable) Register is used to control the gain of the
PNLCLK PFD and spread spectrum. (To select values, see Section 7.3, “Programming Spread Spectrum”.)
Table 6-21.
PNLCLK-SSOE Register
Bit
Bit Name
Bit Definition
Ac-
cess
Spec.
Func.
Re-
set
24:7-
24:6
PNLCLK_SS
[1-0]
PNLCLK Spread-Spectrum (Gain Select) [1-0].
These bits determine the PNLCLK spread-spectrum gain.
0 = The gain is 1.
1 = The gain is 2.
2 = The gain is 4.
3 = The gain is 8.
R/W
D-PK
0
24:5
Reserved
Reserved.
See Section 6.1, “Reserved Bits”.
This bit can be programmed to ‘0’.
––
0
24:4-
24:2
PNLCLK_PFD
[2-0]
PNLCLK Phase/Frequency Detector (Gain Select) [2-0].
These bits determine the PNLCLK Phase/Frequency
Detector gain.
0 = The gain is 1.
1 = The gain is 2.
2 = The gain is 4.
3 = The gain is 8.
4 = The gain is 16, and so forth.
R/W
D-PK
0
24:1-
24:0
PNLCLK_OSD
[1-0]
PNLCLK Output Scaler Divider (Value) [1-0].
These bits determine the value for dividing the PNLCLK
output scaler as follows:
0 = Division is by 1.
1 = Division is by 2.
2 = Division is by 4.
3 = Division is by 8.
R/W
D-PK
0



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