ICS1531 datasheet(67/76 Pages) ICST

Part #	ICS1531

Description	Triple 8-bit MSPS A/D Converters with Line-Locked Clock Generator

PDF	76 Pages

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Manufacturer	ICST [Integrated Circuit Systems]

Direct Link	http://www.icst.com

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Chapter 10

Timing Diagrams

ICS1531 Rev N 12/1/99

December, 1999

ICS1531 Data Sheet - Preliminary

10.3

AC Timing Diagrams

10.3.1

Phase-Locked-Loop Timing for Digital Setup and Hold

The input HSYNC signal is used to generate the REF output signal. In the Phase/Frequency Detector, the

REF signal is compared with ADCSYNC (which provides the recovered HSYNC signal). Table 10-3 gives

the timing for these signals, and Figure 10-5 shows timing characteristics.

Figure 10-5.

Timing for Phase-Locked Loop

Table 10-3.

Phase-Locked-Loop Timing

Time

Period

Timing Description

Min

Typ

Max

Units

Input HSYNC Rise Time to

REF Rise Time

TBD

Clock Period

Clock Duty Cycle

45-55

50-50

55-45

ADCSYNC Active Time

× Tp

Input HSYNC Frequency

Result from:

Section 6.5.3, “Register 02h:

Fdbk Div 0 Register” and

Section 6.5.4, “Register 03h:

Fdbk Div 1 Register”

HSYNC

CLK

ADCSYNC

REF

ICS1531 Datasheet(PDF) 67 Page - Integrated Circuit Systems

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