ICS1531 datasheet(47/76 Pages) ICST

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Chapter 6

ICS1531 Rev N 12/1/99

December, 1999

ICS1531 Data Sheet - Preliminary

6.5.32

The ADC CTRL (Analog-to-Digital Converter Control) Register is used to control the ADC.

Table 6-31.

ADC CTRL Register

Bit

Bit Name

Bit Definition

Ac-

cess

Spec.

Func.

Re-

set

30:7

ADC_OE

Analog-to-Digital Converter (Digital) Outputs Enable.

This bit enables the ADC digital outputs.

• 0 = The ADC digital outputs are disabled.

(The ICS1531 output pads are high-impedance.)

• 1 = The ADC digital outputs are enabled.

(The polarity is controlled by Reg 30:5.)

R/W

–

30:6

ADC_Sel

Analog-to-Digital Converter (Capture) Select.

This bit selects a mode for the ADC.

• 0 =

– The clock rate is 2 pixels per clock (half-rate clock).

– Both the ‘A’ and ‘B’ channels each provide 24-bit pixels

(48 bits total).

• 1 =

– The clock rate is 1 pixel per clock (full-rate clock).

– The ‘A’ channel provides 24-bit pixels (24 bits total).

– The ‘B’ channel is driven either high or low, depending

on the value of Reg 30:5 (ADC_INV).

R/W

–

30:5

ADC_Inv

Analog-to-Digital Converter (Output) Invert (Disable).

This bit disables the inversion of the ADC outputs.

• 0 = The ADC outputs are inverted.

• 1 = The ADC outputs are not inverted (default).

R/W

–

30:4

Force_ADC

Force Analog-to-Digital Converter (Outputs).

This bit forces to ‘off’ all output buffers for the ADC pin.

• 0 = Normal operation

• 1 = Force all ADC output buffers low or high as follows:

– Reg 30:5 = 0 to force buffers low

– Reg 30:5 = 1 to force buffers high

R/W

–

30:3

CLAMP_Pol

Clamp Polarity.

This bit selects the polarity of the signal to a clamp.

• 0 = The polarity of the signal to a clamp is positive.

• 1 = The polarity of the signal to a clamp is negative.

R/W

–

30:2

CLAMP_Sel

Clamp (Source) Select.

This bit selects the source of the signal to a clamp.

• 0 = The source of the signal is internally generated.

• 1 = The source of the signal is from the CLAMP pin.

R/W

–

30:1

VA_Disable

Video Amplifier Disable.

• 0 = Video amplifier is enabled (default).

• 1 = Video amplifier is disabled to conserve power.

––

30:0

FA_Disable

Fine Adjust Disable.

• 0 = The DACs are enabled and they drive the VRTR,

VRTG, and VRTB pins internally.

• 1 = The DACs are disabled and the VRTR, VRTG, and

VRTB pins must be driven externally with ADC top

reference voltage.

R/W

–

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