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ICS1531 Datasheet(PDF) 1 Page - Integrated Circuit Systems |
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ICS1531 Datasheet(HTML) 1 Page - Integrated Circuit Systems |
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1 / 76 page  ICS1531 Rev N 12/1/99 December, 1999 December 8, 2000 2:31pm PRODUCT PREVIEW documents contain information on new products in the sampling or preproduction phase of development. Characteristic data and other specifications are subject to change without notice. Integrated Circuit Systems, Inc. Triple 8-bit MSPS A/D Converters with Line-Locked Clock Generator ICS1531 1531 Document Type: Data Sheet Document Stage: Preliminary Product Preview Features • 3-channel 8-bit analog-to-digital conversion up to 165 MHz • Direct connection to analog input data (no external pre-amplifier circuit needed) • Video amplifier: 500-MHz analog bandwidth, software-adjustable gain • Dynamic Phase Adjust (DPA) for software-adjustable analog sample points • Software selectable: One pixel per clock (for 24-bit pixels) or two pixels per clock (for a total of 48 bits) • Internal clamp circuit. Very low jitter. • Low-voltage TTL clock outputs, synchronized with digital pixel data outputs • Independent software reset for PLLs and DPA • Double-buffered PLL and DPA control registers • Two additional PLLs with spread spectrum for memory and panel clock • External/internal loop-filter selection with software • Automatic Power-On Reset (POR) detection • Uses 3.3 VDC. Digital inputs are 5-V tolerant. • Industry-standard 2-wire serial bus interface speeds: low (100 kHz), high (400 kHz), or ultra (800 kHz) • Lock detection available in hardware and software • 144-pin low-profile quad flat pack (LQFP) package Applications • LCD displays, LCD projectors, plasma displays, and projection TVs General Description The ICS1531 is a high-performance, cost-effective, 3-channel, 8-bit analog-to-digital converter with an integrated line-locked clock generator. It is part of a family of chips intended for high-resolution video applications that use analog inputs, such as LCD monitors, LCD projectors, plasma displays, and projection TVs. Using IC S's low-voltage CMOS mixed-signal technology, the ICS1531 is an effective data-capture solution for resolutions from VGA to UXGA. The ICS1531 offers analog-to-digital data conversion and synchronized pixel clock generation at speeds of 100, 140, or 165 MHz (or mega samples per second, MSPS). The Dynamic Phase Adjust (DPA) circuitry allows end-user control over the pixel clock phase, relative to the recovered sync signal and analog pixel data. Either the internal pixel c lock can be use d as a capt ure cl ock i nput t o the analog-to-digital converters or an external clock input can be used. The ICS1531 provides either one or two 24-bit pixels per clock. An ADCSYNC output pin provides recovered HSYNC from the pixel clock phase-locked-loop (PLL) divider chain output, which can be used to synchronize display enable output. A clamp signal can be generated internally or provided through the CLAMP pin. A high-bandwidth video amplifier with adjustable gain allows fine tuning of the analog signal. The advanced PLL uses an internal programmable feedback divider. Two additional, independent programmable PLLs, each with spread-spectrum functionality, support memory and panel clock requirements. ICS1531 Functional Block Diagram PLL DPA PLL Sp rea d S pectrum POR Serial IF PLL ADC Crystal Oscillator Re d Gre en Blue HSY N C SD A SC L XTAL In XTAL O u t RA0 -R A 7 RB0 -R B 7 GA0 -GA7 GB0 -GB7 BA 0 -B A 7 BB 0 -B B 7 MC LK PN LC LK REF ADCR CLK ADC ADC VS Y N C Sp rea d S pectrum CLAM P CLAM P CLAM P ADCS YN C |
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