ICS1531 datasheet(69/76 Pages) ICST

Part #	ICS1531

Description	Triple 8-bit MSPS A/D Converters with Line-Locked Clock Generator

PDF	76 Pages

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Manufacturer	ICST [Integrated Circuit Systems]

Direct Link	http://www.icst.com

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69 / 76 page

Chapter 10

Timing Diagrams

ICS1531 Rev N 12/1/99

December, 1999

ICS1531 Data Sheet - Preliminary

10.3.3

One-Pixel-per-Clock Mode Timing

For 1-pixel-per-clock mode, Reg 30:6 must be set to ‘1’. Table 10-6 lists time measures for this mode, and

Figure 10-5 shows timing characteristics.

Note:

For the 1-pixel-per-clock mode, the ‘B’ channel data outputs are always at ground level.

Figure 10-7.

AC Timing for 1-Pixel-per-Clock Mode

Table 10-6.

Timing for 1-Pixel-per-Clock Mode

Time

Period

Timing Description

Min

Typ

Max

Units

Tp, Td

CLK Period, CLK Duty Cycle

–

See Table 10-3.–

ACDRCLK Period

–

t1 = Tp

–

ADCRCLK Fall Time to ADCSYNC Rise Time

–

TBD

–ns

Digital Data Transition

2.0

2.5

P-5

P-4

P-1

P+1

P+2

P-6

P+3

P+4

P+5

P-3

P-2

Tp, Td

‘A’ Channel Digital

Data Output

CLK

Analog Data In:

ARED

AGRN

ABLUE

‘B’ Channel Digital

Data Output

ADCSYNC

ADCRCLK

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