AM3874 datasheet(175/361 Pages) TI

175 / 361 page

AM3874, AM3871

www.ti.com

SPRS695C – SEPTEMBER 2011 – REVISED DECEMBER 2013

7.2.4

SERDES_CLKP and SERDES_CLKN LDO

The SERDES_CLKP and SERDES_CLKN input buffers are powered by an internal LDO which is

programmed through the REFCLK_LJCBLDO_CTRL register in the Control Module.

For more information on programming the SERDES_CLKP and SERDES_CLKN LDO, see PCI Express

(PCIe) Module and Serial ATA (SATA) Controller chapters of the AM387x Sitara™ ARM Processors

Technical Reference Manual (Literature Number: SPRUGZ7).

7.2.5

Dual Voltage I/Os

The device supports dual voltages on some of its I/Os. These I/Os are partitioned into the following

groups, and each group has its own dedicated supply pins: DVDD, DVDD_GPMC, DVDD_C, and

DVDD_SD. The supply voltage for each group can be independently powered with either 1.8 V or 3.3 V.

For the mapping between pins and power groups, see Section 3.2, Terminal Functions of the datasheet.

In addition, the I/O voltage on each DDR interface is independently selectable between either 1.5 V or 1.8

V to support various DDR device types. The I/O supplies for each DDR interface are separate and isolated

to allow populating different memory types on each interface.

7.2.6

I/O Power-Down Modes

On the device, there are power-down modes available for the following PHYs:

•

Video DAC

•

DDR

•

USB

•

HDMI

•

PCIE

•

SATA

When a PHY controller is in a power domain that is to be turned "OFF", software must configure the

corresponding PHY into power-down mode, prior to putting the power domain in the "OFF" state.

Power, Reset, Clocking, and Interrupts

175

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AM3874 Datasheet(PDF) 175 Page - Texas Instruments